From 6dc669a22c77ad9c812bef82e186b3ab254470cb Mon Sep 17 00:00:00 2001 From: Jacob Siverskog Date: Fri, 20 Nov 2015 19:03:13 +0100 Subject: [PATCH] clk: si5351: Add PLL soft reset This is according to figure 12 ("I2C Programming Procedure") in "Si5351A/B/C Data Sheet" (https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf). Without the PLL soft reset, we were unable to get three outputs working at the same time. According to Silicon Labs support, performing PLL soft reset will only be noticeable if the PLL parameters have been changed. Signed-off-by: Jacob Siverskog Signed-off-by: Jens Rudberg Acked-by: Sebastian Hesselbarth Signed-off-by: Stephen Boyd --- drivers/clk/clk-si5351.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index e346b223199d..850316ac8831 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -1091,6 +1091,13 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate, si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, SI5351_CLK_POWERDOWN, 0); + /* + * Do a pll soft reset on both plls, needed in some cases to get + * all outputs running. + */ + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + SI5351_PLL_RESET_A | SI5351_PLL_RESET_B); + dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", __func__, clk_hw_get_name(hw), (1 << rdiv), -- 2.11.0