From 6e554074955b453e8c8d671ec523d273703f2a59 Mon Sep 17 00:00:00 2001 From: Akshu Agrawal Date: Tue, 8 May 2018 10:17:51 +0530 Subject: [PATCH] ASoC: AMD: Fix clocks in CZ DA7219 machine driver System clock on the platform is 25Mhz and not 24Mhz. PLL_OUT for da7219 codec to use DA7219_PLL_FREQ_OUT_98304 as it is for 48KHz SR. Signed-off-by: Akshu Agrawal Signed-off-by: Vijendar Mukunda Reviewed-by: Daniel Kurtz Signed-off-by: Mark Brown --- sound/soc/amd/acp-da7219-max98357a.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/sound/soc/amd/acp-da7219-max98357a.c b/sound/soc/amd/acp-da7219-max98357a.c index 6495eedc3d4c..fa5ad5b468a2 100644 --- a/sound/soc/amd/acp-da7219-max98357a.c +++ b/sound/soc/amd/acp-da7219-max98357a.c @@ -39,8 +39,7 @@ #include "../codecs/da7219.h" #include "../codecs/da7219-aad.h" -#define CZ_PLAT_CLK 24000000 -#define MCLK_RATE 24576000 +#define CZ_PLAT_CLK 25000000 #define DUAL_CHANNEL 2 static struct snd_soc_jack cz_jack; @@ -63,7 +62,7 @@ static int cz_da7219_init(struct snd_soc_pcm_runtime *rtd) } ret = snd_soc_dai_set_pll(codec_dai, 0, DA7219_SYSCLK_PLL, - CZ_PLAT_CLK, MCLK_RATE); + CZ_PLAT_CLK, DA7219_PLL_FREQ_OUT_98304); if (ret < 0) { dev_err(rtd->dev, "can't set codec pll: %d\n", ret); return ret; -- 2.11.0