From 6eb219e963be879d807969d81c30618d373028f8 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 22 May 2019 18:21:55 -0400 Subject: [PATCH] radeonsi/gfx10: fix intensity formats move the ALPHA_IS_ON_MSB fixup into vi_alpha_is_on_msb Acked-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_clear.c | 18 ++++++++++++------ src/gallium/drivers/radeonsi/si_descriptors.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.h | 5 +++-- src/gallium/drivers/radeonsi/si_state.c | 4 ++-- src/gallium/drivers/radeonsi/si_texture.c | 8 +++++--- 5 files changed, 23 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index fa8ae5d2566..9a32977243c 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -99,18 +99,23 @@ enum pipe_format si_simplify_cb_format(enum pipe_format format) return util_format_intensity_to_red(format); } -bool vi_alpha_is_on_msb(enum pipe_format format) +bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format) { format = si_simplify_cb_format(format); + const struct util_format_description *desc = util_format_description(format); /* Formats with 3 channels can't have alpha. */ - if (util_format_description(format)->nr_channels == 3) + if (desc->nr_channels == 3) return true; /* same as xxxA; is any value OK here? */ + if (sscreen->info.chip_class >= GFX10 && desc->nr_channels == 1) + return desc->swizzle[3] == PIPE_SWIZZLE_X; + return si_translate_colorswap(format, false) <= 1; } -static bool vi_get_fast_clear_parameters(enum pipe_format base_format, +static bool vi_get_fast_clear_parameters(struct si_screen *sscreen, + enum pipe_format base_format, enum pipe_format surface_format, const union pipe_color_union *color, uint32_t* clear_value, @@ -142,8 +147,8 @@ static bool vi_get_fast_clear_parameters(enum pipe_format base_format, if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) return true; /* need ELIMINATE_FAST_CLEAR */ - bool base_alpha_is_on_msb = vi_alpha_is_on_msb(base_format); - bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(surface_format); + bool base_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, base_format); + bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, surface_format); /* Formats with 3 channels can't have alpha. */ if (desc->nr_channels == 3) @@ -483,7 +488,8 @@ static void si_do_fast_color_clear(struct si_context *sctx, !tex->surface.u.legacy.level[level].dcc_fast_clear_size) continue; - if (!vi_get_fast_clear_parameters(tex->buffer.b.b.format, + if (!vi_get_fast_clear_parameters(sctx->screen, + tex->buffer.b.b.format, fb->cbufs[i]->format, color, &reset_value, &eliminate_needed)) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index a997bd4febf..006656ddc2e 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -739,7 +739,7 @@ static void si_set_shader_image_desc(struct si_context *ctx, if (uses_dcc && !skip_decompress && (view->access & PIPE_IMAGE_ACCESS_WRITE || - !vi_dcc_formats_compatible(res->b.b.format, view->format))) { + !vi_dcc_formats_compatible(screen, res->b.b.format, view->format))) { /* If DCC can't be disabled, at least decompress it. * The decompression is relatively cheap if the surface * has been decompressed already. diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index e3c9151e87e..06508beb9f2 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1265,7 +1265,7 @@ void si_init_buffer_functions(struct si_context *sctx); /* si_clear.c */ enum pipe_format si_simplify_cb_format(enum pipe_format format); -bool vi_alpha_is_on_msb(enum pipe_format format); +bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format); void vi_dcc_clear_level(struct si_context *sctx, struct si_texture *tex, unsigned level, unsigned clear_value); @@ -1486,7 +1486,8 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex, struct u_log_context *log); struct pipe_resource *si_texture_create(struct pipe_screen *screen, const struct pipe_resource *templ); -bool vi_dcc_formats_compatible(enum pipe_format format1, +bool vi_dcc_formats_compatible(struct si_screen *sscreen, + enum pipe_format format1, enum pipe_format format2); bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, unsigned level, diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 68ba7d6403e..d4b7aabd5ce 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3979,7 +3979,7 @@ gfx10_make_texture_descriptor(struct si_screen *screen, if (tex->dcc_offset) { state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) | S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) | - S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format)); + S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format)); } /* Initialize the sampler view for FMASK. */ @@ -4260,7 +4260,7 @@ si_make_texture_descriptor(struct si_screen *screen, } if (tex->dcc_offset) { - state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format)); + state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format)); } else { /* The last dword is unused by hw. The shader uses it to clear * bits in the first dword of sampler state. diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 6e96b66f8a4..7b72e51065c 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -2056,7 +2056,8 @@ static const struct u_resource_vtbl si_texture_vtbl = /* Return if it's allowed to reinterpret one format as another with DCC enabled. */ -bool vi_dcc_formats_compatible(enum pipe_format format1, +bool vi_dcc_formats_compatible(struct si_screen *sscreen, + enum pipe_format format1, enum pipe_format format2) { const struct util_format_description *desc1, *desc2; @@ -2098,7 +2099,7 @@ bool vi_dcc_formats_compatible(enum pipe_format format1, /* If the clear values are all 1 or all 0, this constraint can be * ignored. */ - if (vi_alpha_is_on_msb(format1) != vi_alpha_is_on_msb(format2)) + if (vi_alpha_is_on_msb(sscreen, format1) != vi_alpha_is_on_msb(sscreen, format2)) return false; /* Channel types must match if the clear value of 1 is used. @@ -2120,7 +2121,8 @@ bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, struct si_texture *stex = (struct si_texture *)tex; return vi_dcc_enabled(stex, level) && - !vi_dcc_formats_compatible(tex->format, view_format); + !vi_dcc_formats_compatible((struct si_screen*)tex->screen, + tex->format, view_format); } /* This can't be merged with the above function, because -- 2.11.0