From 6f4104b7f2e43154552e19bc1a774f0b28791591 Mon Sep 17 00:00:00 2001 From: yujiro_kaeko Date: Mon, 7 Nov 2011 20:46:33 +0900 Subject: [PATCH] =?utf8?q?vga=5Ftop=E4=BF=AE=E6=AD=A3=E3=83=90=E3=83=BC?= =?utf8?q?=E3=82=B8=E3=83=A7=E3=83=B3=20=E3=83=81=E3=82=A7=E3=83=83?= =?utf8?q?=E3=82=AF=E6=9F=84=E5=87=BA=E5=8A=9B=E7=A2=BA=E8=AA=8D=E3=80=82?= =?utf8?q?=20=E3=82=A2=E3=83=89=E3=83=AC=E3=82=B9=E3=81=AE=E3=81=9A?= =?utf8?q?=E3=82=8C=E3=81=8C=E7=99=BA=E7=94=9F=E3=81=97=E3=81=A6=E7=94=BB?= =?utf8?q?=E9=9D=A2=E3=81=8C=E3=82=B9=E3=83=A9=E3=82=A4=E3=83=89=E3=81=99?= =?utf8?q?=E3=82=8B=E3=81=AE=E3=81=A7=E3=80=81=20=E3=82=A2=E3=83=89?= =?utf8?q?=E3=83=AC=E3=82=B9=E8=A8=88=E7=AE=97=E3=81=AE=E9=83=A8=E5=88=86?= =?utf8?q?=E3=82=92=E4=BF=AE=E6=AD=A3=E3=80=82=20=E6=9C=AA=E6=A4=9C?= =?utf8?q?=E8=A8=BC?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Change-Id: If4d80dba6efc7b212d05f5d9fa4f482ee91b6b34 --- VGADisplay/src/push_sw.nsl | 46 ++++++++++++++++++++++++++++++++++++++++++++++ VGADisplay/src/vga_gen.nsl | 13 +++++++++++-- VGADisplay/src/vga_ram.v | 11 +++++++---- VGADisplay/src/vga_top.nsl | 34 +++++++++++++++++++--------------- 4 files changed, 83 insertions(+), 21 deletions(-) create mode 100644 VGADisplay/src/push_sw.nsl diff --git a/VGADisplay/src/push_sw.nsl b/VGADisplay/src/push_sw.nsl new file mode 100644 index 0000000..2277089 --- /dev/null +++ b/VGADisplay/src/push_sw.nsl @@ -0,0 +1,46 @@ +/** +* Push switch module +* Module name "push_sw" +* @author Yujiro Kaneko +* @version 0.1 +*/ + +#define CNT_1ms 19'd500000 // Count value for 1m sec at 50MHz +//#define CNT_1ms 26'd50 // Count value for test + +#define TRUE 1'd1 +#define FALSE 1'd0 + +declare push_sw { + input i_sw ; // Button signal input terminal + func_out fo_sw_enb ; // Button enable signal +} +module push_sw { + reg r_cnt[19] = 19'd0 ; // Button enable count + reg r_rise_flag = FALSE ; // Button signal rising flag + reg r_sw_hld = 0 ; // + reg r_finish_flag = FALSE ; // "fo_btn_enb" transfer flag + + r_sw_hld := i_sw ; + + if( i_sw & ~r_sw_hld ) { + r_rise_flag := TRUE ; + } else if( ~i_sw ) { + r_rise_flag := FALSE ; + r_finish_flag := FALSE ; + } + + if( r_rise_flag == TRUE ){ + any { + ( r_cnt == CNT_1ms ) & ( r_finish_flag == FALSE ) : { + r_finish_flag := TRUE ; + fo_sw_enb() ; + } + else : { + r_cnt++ ; + } + } + } else { + r_cnt := 26'd0 ; + } +} \ No newline at end of file diff --git a/VGADisplay/src/vga_gen.nsl b/VGADisplay/src/vga_gen.nsl index 8d4970c..1d099c4 100644 --- a/VGADisplay/src/vga_gen.nsl +++ b/VGADisplay/src/vga_gen.nsl @@ -114,7 +114,7 @@ module vga_gen { // HACTMAX640 VACTMAX480 ƒJƒ‰[•`‰æƒGƒŠƒA - if( ( r_hcnt < H_ACT_MAX ) && ( r_vcnt < V_ACT_MAX ) ) { + if( ( r_hcnt < H_ACT_MAX ) && ( r_vcnt < V_ACT_MAX ) && r_vsync ) { // ƒf[ƒ^ƒoƒbƒtƒ@‰^—pƒJƒEƒ“ƒ^iƒeƒXƒg—pj if( r_init_flg ) { @@ -175,6 +175,14 @@ module vga_gen { r_hsync := 1 ; } } + + // FIFO“ǂݏo‚µ’lƒoƒbƒtƒ@ƒŠƒ“ƒO + if( fs_fifo_ack ) { + any { + ~r_reg_cnt : r_data2 := w_rddata ; + r_reg_cnt : r_data1 := w_rddata ; + } + } } any { @@ -182,7 +190,8 @@ module vga_gen { r_vcnt == V_FRONTP_MAX : r_vsync := 0 ; r_vcnt == V_SYNC_MAX : r_vsync := 1 ; } - } + + } // public end ; // VGA Gen initialize command func fs_initialize seq { diff --git a/VGADisplay/src/vga_ram.v b/VGADisplay/src/vga_ram.v index ea2bf3a..70bef6e 100644 --- a/VGADisplay/src/vga_ram.v +++ b/VGADisplay/src/vga_ram.v @@ -23,10 +23,10 @@ module vga_ram ( (* remstyle = "no_rw_check" *) reg [7:0] mem1[511:0] ; assign o_rddata = mem1[r_rdadrs] ; - assign o_rdack = (r_rdadrs_buff != r_rdadrs[9]) ; + assign o_rdack = (r_rdadrs_buff != r_rdadrs[8]) ; always @( posedge i_clk50 ) begin - r_rdadrs_buff <= r_rdadrs[9] ; + r_rdadrs_buff <= r_rdadrs[8] ; end // memory read command @@ -35,7 +35,8 @@ module vga_ram ( r_rdadrs <= 0 ; end else if( i_re ) begin - r_rdadrs <= r_rdadrs + 9'd1 ; + if(r_rdadrs < 480) r_rdadrs <= r_rdadrs + 9'd1 ; + else r_rdadrs <= 9'd0 ; end end @@ -46,7 +47,9 @@ module vga_ram ( end else if( i_we ) begin mem1[r_wradrs] <= i_wrdata ; - r_wradrs <= r_wradrs + 9'd1 ; + + if(r_wradrs < 480) r_wradrs <= r_wradrs + 9'd1 ; + else r_wradrs <= 9'd0 ; end end endmodule \ No newline at end of file diff --git a/VGADisplay/src/vga_top.nsl b/VGADisplay/src/vga_top.nsl index 6291e3f..cd212fd 100644 --- a/VGADisplay/src/vga_top.nsl +++ b/VGADisplay/src/vga_top.nsl @@ -111,18 +111,18 @@ module vga_top { trigger := { trigger[1:0], 0b1 } ; if(trigger == 3'b011) fs_init() ; -/* - if(~r_reset) { - any { - r_hld_vram_start & ~u_VGA.o_vcnt[0] : { //FIFO1‚ð“ǂݏo‚·ƒ^ƒCƒ~ƒ“ƒO - if(u_VGA.o_vcnt < 10'd480) fs_fifo2_charge() ; - } - ~r_hld_vram_start & u_VGA.o_vcnt[0] : { //FIFO2‚ð“ǂݏo‚·ƒ^ƒCƒ~ƒ“ƒO - if(u_VGA.o_vcnt < 10'd480) fs_fifo1_charge() ; - } - } - } -*/ + +// if(~r_reset) { +// any { +// r_hld_vram_start & ~u_VGA.o_vcnt[0] : { //FIFO1‚ð“ǂݏo‚·ƒ^ƒCƒ~ƒ“ƒO +// if(u_VGA.o_vcnt < 10'd480) fs_fifo2_charge() ; +// } +// ~r_hld_vram_start & u_VGA.o_vcnt[0] : { //FIFO2‚ð“ǂݏo‚·ƒ^ƒCƒ~ƒ“ƒO +// if(u_VGA.o_vcnt < 10'd480) fs_fifo1_charge() ; +// } +// } +// } + any { r_sec_cnt == CNT1S : { @@ -192,9 +192,13 @@ module vga_top { r_fifo_rst := 0 ; ;;; - for(r_init_cnt:=0; r_init_cnt<512; r_init_cnt++ ) { - u_VGA.fi_fifo_write(r_init_cnt[7:0]) ; - u_VGA.fi_fifo_write(r_init_cnt[7:0]) ; + for(r_init_cnt:=0; r_init_cnt<120; r_init_cnt++ ) { + u_VGA.fi_fifo_write(8'hFF) ; + u_VGA.fi_fifo_write(8'h00) ; + } + for(r_init_cnt:=0; r_init_cnt<120; r_init_cnt++ ) { + u_VGA.fi_fifo_write(8'h00) ; + u_VGA.fi_fifo_write(8'hFF) ; } r_reset := 0 ; -- 2.11.0