From 723ef71dbf4ab714a0fa9f197dab6f1896adaa6f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 29 Jun 2017 11:09:53 +0000 Subject: [PATCH] [X86][SSE] Dropped -mcpu from vector shift tests Use triple and attribute only for consistency git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306662 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/lower-vec-shift.ll | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/test/CodeGen/X86/lower-vec-shift.ll b/test/CodeGen/X86/lower-vec-shift.ll index 783cda0a8dd..8d64baf5f2a 100644 --- a/test/CodeGen/X86/lower-vec-shift.ll +++ b/test/CodeGen/X86/lower-vec-shift.ll @@ -1,8 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1 -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2 - +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+ssse3 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2 ; Verify that the following shifts are lowered into a sequence of two shifts plus ; a blend. On pre-avx2 targets, instead of scalarizing logical and arithmetic -- 2.11.0