From 72c0afef177efc8af3a06d63b63cda41243e1325 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 7 May 2018 16:34:26 +0000 Subject: [PATCH] [X86][Znver1] Remove WriteFMul/WriteFRcp InstRW overrides/aliases. Fixes x87 schedules to more closely match Agner - AMD doesn't tend to "special case" x87 instructions as much as Intel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331645 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ScheduleZnver1.td | 47 ++------------------------ test/CodeGen/X86/x87-schedule.ll | 16 ++++----- test/tools/llvm-mca/X86/Znver1/resources-x87.s | 34 +++++++++---------- 3 files changed, 28 insertions(+), 69 deletions(-) diff --git a/lib/Target/X86/X86ScheduleZnver1.td b/lib/Target/X86/X86ScheduleZnver1.td index 5c3408b93c0..c2325577962 100644 --- a/lib/Target/X86/X86ScheduleZnver1.td +++ b/lib/Target/X86/X86ScheduleZnver1.td @@ -223,14 +223,14 @@ defm : ZnWriteResFpuPair; defm : ZnWriteResFpuPair; defm : ZnWriteResFpuPair; defm : ZnWriteResFpuPair; -defm : ZnWriteResFpuPair; -defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; defm : ZnWriteResFpuPair; defm : ZnWriteResFpuPair; defm : ZnWriteResFpuPair; defm : ZnWriteResFpuPair; defm : ZnWriteResFpuPair; -//defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; //defm : ZnWriteResFpuPair; defm : ZnWriteResFpuPair; //defm : ZnWriteResFpuPair; @@ -1460,32 +1460,6 @@ def : SchedAlias; def : SchedAlias; def : SchedAlias; -// MULL SS/SD PS/PD. -// x,x / v,v,v. -def ZnWriteMULr : SchedWriteRes<[ZnFPU01]> { - let Latency = 3; -} -// ymm. -def ZnWriteMULYr : SchedWriteRes<[ZnFPU01]> { - let Latency = 4; -} -def : InstRW<[ZnWriteMULr], (instregex "(V?)MUL(P|S)(S|D)rr")>; -def : InstRW<[ZnWriteMULYr], (instregex "(V?)MUL(P|S)(S|D)Yrr")>; - -// x,m / v,v,m. -def ZnWriteMULLd : SchedWriteRes<[ZnAGU, ZnFPU01]> { - let Latency = 10; - let NumMicroOps = 2; -} -def : InstRW<[ZnWriteMULLd], (instregex "(V?)MUL(P|S)(S|D)rm")>; - -// ymm -def ZnWriteMULYLd : SchedWriteRes<[ZnAGU, ZnFPU01]> { - let Latency = 11; - let NumMicroOps = 2; -} -def : InstRW<[ZnWriteMULYLd], (instregex "(V?)MUL(P|S)(S|D)Yrm")>; - // VDIVPS. // TODO - convert to ZnWriteResFpuPair // y,y,y. @@ -1520,21 +1494,6 @@ def ZnWriteVDIVPDYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { } def : SchedAlias; -// VRCPPS. -// TODO - convert to ZnWriteResFpuPair -// y,y. -def ZnWriteVRCPPSYr : SchedWriteRes<[ZnFPU01]> { - let Latency = 5; -} -def : SchedAlias; - -// y,m256. -def ZnWriteVRCPPSYLd : SchedWriteRes<[ZnAGU, ZnFPU01]> { - let Latency = 12; - let NumMicroOps = 3; -} -def : SchedAlias; - // DPPS. // x,x,i / v,v,v,i. def : SchedAlias; diff --git a/test/CodeGen/X86/x87-schedule.ll b/test/CodeGen/X86/x87-schedule.ll index e8113e14ae1..428570652d0 100644 --- a/test/CodeGen/X86/x87-schedule.ll +++ b/test/CodeGen/X86/x87-schedule.ll @@ -3067,10 +3067,10 @@ define void @test_fmul(float *%a0, double *%a1) optsize { ; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50] ; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50] ; ZNVER1-NEXT: #APP -; ZNVER1-NEXT: fmul %st(0), %st(1) # sched: [5:1.00] -; ZNVER1-NEXT: fmul %st(2) # sched: [5:1.00] -; ZNVER1-NEXT: fmuls (%ecx) # sched: [12:1.00] -; ZNVER1-NEXT: fmull (%eax) # sched: [12:1.00] +; ZNVER1-NEXT: fmul %st(0), %st(1) # sched: [3:0.50] +; ZNVER1-NEXT: fmul %st(2) # sched: [3:0.50] +; ZNVER1-NEXT: fmuls (%ecx) # sched: [10:0.50] +; ZNVER1-NEXT: fmull (%eax) # sched: [10:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retl # sched: [1:0.50] tail call void asm sideeffect "fmul %st(0), %st(1) \0A\09 fmul %st(2), %st(0) \0A\09 fmuls $0 \0A\09 fmull $1", "*m,*m"(float *%a0, double *%a1) nounwind @@ -3191,10 +3191,10 @@ define void @test_fmulp_fimul(i16 *%a0, i32 *%a1) optsize { ; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50] ; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50] ; ZNVER1-NEXT: #APP -; ZNVER1-NEXT: fmulp %st(1) # sched: [5:1.00] -; ZNVER1-NEXT: fmulp %st(2) # sched: [5:1.00] -; ZNVER1-NEXT: fimuls (%ecx) # sched: [12:1.00] -; ZNVER1-NEXT: fimull (%eax) # sched: [12:1.00] +; ZNVER1-NEXT: fmulp %st(1) # sched: [3:0.50] +; ZNVER1-NEXT: fmulp %st(2) # sched: [3:0.50] +; ZNVER1-NEXT: fimuls (%ecx) # sched: [10:0.50] +; ZNVER1-NEXT: fimull (%eax) # sched: [10:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retl # sched: [1:0.50] tail call void asm sideeffect "fmulp \0A\09 fmulp %st(2), %st(0) \0A\09 fimuls $0 \0A\09 fimull $1", "*m,*m"(i16 *%a0, i32 *%a1) nounwind diff --git a/test/tools/llvm-mca/X86/Znver1/resources-x87.s b/test/tools/llvm-mca/X86/Znver1/resources-x87.s index 9db502c6c4e..11ca3a1c456 100644 --- a/test/tools/llvm-mca/X86/Znver1/resources-x87.s +++ b/test/tools/llvm-mca/X86/Znver1/resources-x87.s @@ -288,14 +288,14 @@ fyl2xp1 # CHECK-NEXT: 1 11 1.00 * fldln2 # CHECK-NEXT: 1 11 1.00 * fldpi # CHECK-NEXT: 1 8 0.50 * fldz -# CHECK-NEXT: 1 5 1.00 * fmul %st(0), %st(1) -# CHECK-NEXT: 1 5 1.00 * fmul %st(2) -# CHECK-NEXT: 1 12 1.00 * * fmuls (%ecx) -# CHECK-NEXT: 1 12 1.00 * * fmull (%eax) -# CHECK-NEXT: 1 5 1.00 * fmulp %st(1) -# CHECK-NEXT: 1 5 1.00 * fmulp %st(2) -# CHECK-NEXT: 1 12 1.00 * * fimuls (%ecx) -# CHECK-NEXT: 1 12 1.00 * * fimull (%eax) +# CHECK-NEXT: 1 3 0.50 * fmul %st(0), %st(1) +# CHECK-NEXT: 1 3 0.50 * fmul %st(2) +# CHECK-NEXT: 2 10 0.50 * * fmuls (%ecx) +# CHECK-NEXT: 2 10 0.50 * * fmull (%eax) +# CHECK-NEXT: 1 3 0.50 * fmulp %st(1) +# CHECK-NEXT: 1 3 0.50 * fmulp %st(2) +# CHECK-NEXT: 2 10 0.50 * * fimuls (%ecx) +# CHECK-NEXT: 2 10 0.50 * * fimull (%eax) # CHECK-NEXT: 1 1 1.00 * fnop # CHECK-NEXT: 1 100 - * fpatan # CHECK-NEXT: 1 100 - * fprem @@ -371,7 +371,7 @@ fyl2xp1 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] -# CHECK-NEXT: 32.50 32.50 - - - - - 58.50 2.00 8.00 64.50 - +# CHECK-NEXT: 32.50 32.50 - - - - - 54.50 6.00 8.00 64.50 - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions: @@ -457,14 +457,14 @@ fyl2xp1 # CHECK-NEXT: 0.50 0.50 - - - - - - - - 1.00 - fldln2 # CHECK-NEXT: 0.50 0.50 - - - - - - - - 1.00 - fldpi # CHECK-NEXT: 0.50 0.50 - - - - - - 0.50 - 0.50 - fldz -# CHECK-NEXT: - - - - - - - 1.00 - - - - fmul %st(0), %st(1) -# CHECK-NEXT: - - - - - - - 1.00 - - - - fmul %st(2) -# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - fmuls (%ecx) -# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - fmull (%eax) -# CHECK-NEXT: - - - - - - - 1.00 - - - - fmulp %st(1) -# CHECK-NEXT: - - - - - - - 1.00 - - - - fmulp %st(2) -# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - fimuls (%ecx) -# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - fimull (%eax) +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmul %st(0), %st(1) +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmul %st(2) +# CHECK-NEXT: 0.50 0.50 - - - - - 0.50 0.50 - - - fmuls (%ecx) +# CHECK-NEXT: 0.50 0.50 - - - - - 0.50 0.50 - - - fmull (%eax) +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmulp %st(1) +# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmulp %st(2) +# CHECK-NEXT: 0.50 0.50 - - - - - 0.50 0.50 - - - fimuls (%ecx) +# CHECK-NEXT: 0.50 0.50 - - - - - 0.50 0.50 - - - fimull (%eax) # CHECK-NEXT: - - - - - - - 1.00 - - - - fnop # CHECK-NEXT: - - - - - - - - - - - - fpatan # CHECK-NEXT: - - - - - - - - - - - - fprem -- 2.11.0