From 72d2da5ca363625bc344d001561f8b4cbd4b50e7 Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Fri, 6 May 2016 21:10:53 +0000 Subject: [PATCH] [X86] Add a new LOW32_ADDR_ACCESS_RBP register class. ABIs like NaCl uses 32-bit addresses but have 64-bit frame. The new register class reflects those constraints when choosing a register class for a address access. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268796 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86RegisterInfo.cpp | 10 +++++++++- lib/Target/X86/X86RegisterInfo.td | 5 +++++ test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll | 6 +++--- 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index e32a5fdcdba..cb4170cc623 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -166,7 +166,15 @@ X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, // we can still use 64-bit register as long as we know the high bits // are zeros. // Reflect that in the returned register class. - return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass; + if (Is64Bit) { + // When the target also allows 64-bit frame pointer and we do have a + // frame, this is fine to use it for the address accesses as well. + const X86FrameLowering *TFI = getFrameLowering(MF); + return TFI->hasFP(MF) && TFI->Uses64BitFramePtr + ? &X86::LOW32_ADDR_ACCESS_RBPRegClass + : &X86::LOW32_ADDR_ACCESSRegClass; + } + return &X86::GR32RegClass; case 1: // Normal GPRs except the stack pointer (for encoding reasons). if (Subtarget.isTarget64BitLP64()) return &X86::GR64_NOSPRegClass; diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index 3c50ac7ce50..d3544beae61 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -427,6 +427,11 @@ def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, // which we do not have right now. def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>; +// When RBP is used as a base pointer in a 32-bit addresses environement, +// this is also safe to use the full register to access addresses. +def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 64, + (add LOW32_ADDR_ACCESS, RBP)>; + // A class to support the 'A' assembler constraint: EAX then EDX. def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; diff --git a/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll b/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll index c476ffd8405..b1f4ca56223 100644 --- a/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll +++ b/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=x86_64-pc-linux < %s | FileCheck %s -; RUN: llc -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s -; RUN: llc -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s +; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s +; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s ; x32 uses %esp, %ebp as stack and frame pointers -- 2.11.0