From 745502a04bc786053e7a19bf7f1266180a6985e9 Mon Sep 17 00:00:00 2001 From: Alkis Evlogimenos Date: Sat, 28 Feb 2004 06:01:43 +0000 Subject: [PATCH] Do not generate instructions with mismatched memory/immediate sized operands. The X86 backend doesn't handle them properly right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11944 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/PeepholeOptimizer.cpp | 6 ++++- lib/Target/X86/X86InstrInfo.td | 46 ++++++++++++++++++------------------ lib/Target/X86/X86PeepholeOpt.cpp | 6 ++++- lib/Target/X86/X86RegisterInfo.cpp | 22 ++++++++--------- 4 files changed, 44 insertions(+), 36 deletions(-) diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp index 1640862270b..b27602af48a 100644 --- a/lib/Target/X86/PeepholeOptimizer.cpp +++ b/lib/Target/X86/PeepholeOptimizer.cpp @@ -156,7 +156,10 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB, } return false; - +// FIXME: The printer currently does not play well with instructions +// that have immediates and memory operands with size mismatches so +// the following are disabled. +#if 0 case X86::ADDmi16: case X86::ADDmi32: case X86::SUBmi16: case X86::SUBmi32: case X86::ANDmi16: case X86::ANDmi32: @@ -192,6 +195,7 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB, } } return false; +#endif #if 0 case X86::MOVri32: Size++; diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 8993d76f111..b9f804c58f7 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -311,8 +311,8 @@ def ADDmi32 : I2A32<"add", 0x81, MRM0m >; // [mem32] += I32 def ADDri16b : I2A8 <"add", 0x83, MRM0r >, OpSize; // ADDri with sign extended 8 bit imm def ADDri32b : I2A8 <"add", 0x83, MRM0r >; -def ADDmi16b : I2A8 <"add", 0x83, MRM0m >, OpSize; // [mem16] += I8 -def ADDmi32b : I2A8 <"add", 0x83, MRM0m >; // [mem32] += I8 +// def ADDmi16b : I2A8 <"add", 0x83, MRM0m >, OpSize; // [mem16] += I8 +// def ADDmi32b : I2A8 <"add", 0x83, MRM0m >; // [mem32] += I8 def ADCrr32 : I2A32<"adc", 0x11, MRMDestReg>; // R32 += R32+Carry def ADCrm32 : I2A32<"adc", 0x11, MRMSrcMem >; // R32 += [mem32]+Carry @@ -337,8 +337,8 @@ def SUBmi32 : I2A32<"sub", 0x81, MRM5m >; // [mem32] -= I32 def SUBri16b : I2A8 <"sub", 0x83, MRM5r >, OpSize; def SUBri32b : I2A8 <"sub", 0x83, MRM5r >; -def SUBmi16b : I2A8 <"sub", 0x83, MRM5m >, OpSize; // [mem16] -= I8 -def SUBmi32b : I2A8 <"sub", 0x83, MRM5m >; // [mem32] -= I8 +// def SUBmi16b : I2A8 <"sub", 0x83, MRM5m >, OpSize; // [mem16] -= I8 +// def SUBmi32b : I2A8 <"sub", 0x83, MRM5m >; // [mem32] -= I8 def SBBrr32 : I2A32<"sbb", 0x19, MRMDestReg>; // R32 -= R32+Borrow def SBBrm32 : I2A32<"sbb", 0x19, MRMSrcMem >; // R32 -= [mem32]+Borrow @@ -357,8 +357,8 @@ def IMULrri16b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8 >, OpSize; // R16 = def IMULrri32b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8 >; // R32 = R32*I8 def IMULrmi16 : X86Inst<"imul", 0x69, MRMSrcMem, Arg16>, OpSize; // R16 = [mem16]*I16 def IMULrmi32 : X86Inst<"imul", 0x69, MRMSrcMem, Arg32>; // R32 = [mem32]*I32 -def IMULrmi16b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >, OpSize; // R16 = [mem16]*I8 -def IMULrmi32b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >; // R32 = [mem32]*I8 +// def IMULrmi16b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >, OpSize; // R16 = [mem16]*I8 +// def IMULrmi32b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >; // R32 = [mem32]*I8 @@ -382,8 +382,8 @@ def ANDmi32 : I2A32<"and", 0x81, MRM4m >; // [mem32] &= imm32 def ANDri16b : I2A8 <"and", 0x83, MRM4r >, OpSize; // R16 &= imm8 def ANDri32b : I2A8 <"and", 0x83, MRM4r >; // R32 &= imm8 -def ANDmi16b : I2A8 <"and", 0x83, MRM4m >, OpSize; // [mem16] &= imm8 -def ANDmi32b : I2A8 <"and", 0x83, MRM4m >; // [mem32] &= imm8 +// def ANDmi16b : I2A8 <"and", 0x83, MRM4m >, OpSize; // [mem16] &= imm8 +// def ANDmi32b : I2A8 <"and", 0x83, MRM4m >; // [mem32] &= imm8 @@ -407,8 +407,8 @@ def ORmi32 : I2A32<"or" , 0x81, MRM1m >; // [mem32] |= imm32 def ORri16b : I2A8 <"or" , 0x83, MRM1r >, OpSize; // R16 |= imm8 def ORri32b : I2A8 <"or" , 0x83, MRM1r >; // R32 |= imm8 -def ORmi16b : I2A8 <"or" , 0x83, MRM1m >, OpSize; // [mem16] |= imm8 -def ORmi32b : I2A8 <"or" , 0x83, MRM1m >; // [mem32] |= imm8 +// def ORmi16b : I2A8 <"or" , 0x83, MRM1m >, OpSize; // [mem16] |= imm8 +// def ORmi32b : I2A8 <"or" , 0x83, MRM1m >; // [mem32] |= imm8 def XORrr8 : I2A8 <"xor", 0x30, MRMDestReg>, Pattern<(set R8 , (xor R8 , R8 ))>; @@ -430,8 +430,8 @@ def XORmi32 : I2A32<"xor", 0x81, MRM6m >; // [mem32] ^= R32 def XORri16b : I2A8 <"xor", 0x83, MRM6r >, OpSize; // R16 ^= imm8 def XORri32b : I2A8 <"xor", 0x83, MRM6r >; // R32 ^= imm8 -def XORmi16b : I2A8 <"xor", 0x83, MRM6m >, OpSize; // [mem16] ^= imm8 -def XORmi32b : I2A8 <"xor", 0x83, MRM6m >; // [mem32] ^= imm8 +// def XORmi16b : I2A8 <"xor", 0x83, MRM6m >, OpSize; // [mem16] ^= imm8 +// def XORmi32b : I2A8 <"xor", 0x83, MRM6m >; // [mem32] ^= imm8 // Test instructions are just like AND, except they don't generate a result. def TESTrr8 : X86Inst<"test", 0x84, MRMDestReg, Arg8 >; // flags = R8 & R8 @@ -464,9 +464,9 @@ def SHLmCL32 : I2A32<"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl def SHLri8 : I2A8 <"shl", 0xC0, MRM4r >; // R8 <<= imm8 def SHLri16 : I2A8 <"shl", 0xC1, MRM4r >, OpSize; // R16 <<= imm8 def SHLri32 : I2A8 <"shl", 0xC1, MRM4r >; // R32 <<= imm8 -def SHLmi8 : I2A8 <"shl", 0xC0, MRM4m >; // [mem8] <<= imm8 -def SHLmi16 : I2A8 <"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8 -def SHLmi32 : I2A8 <"shl", 0xC1, MRM4m >; // [mem32] <<= imm8 +// def SHLmi8 : I2A8 <"shl", 0xC0, MRM4m >; // [mem8] <<= imm8 +// def SHLmi16 : I2A8 <"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8 +// def SHLmi32 : I2A8 <"shl", 0xC1, MRM4m >; // [mem32] <<= imm8 def SHRrCL8 : I2A8 <"shr", 0xD2, MRM5r > , UsesCL; // R8 >>= cl def SHRrCL16 : I2A16<"shr", 0xD3, MRM5r >, OpSize, UsesCL; // R16 >>= cl @@ -478,9 +478,9 @@ def SHRmCL32 : I2A32<"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl def SHRri8 : I2A8 <"shr", 0xC0, MRM5r >; // R8 >>= imm8 def SHRri16 : I2A8 <"shr", 0xC1, MRM5r >, OpSize; // R16 >>= imm8 def SHRri32 : I2A8 <"shr", 0xC1, MRM5r >; // R32 >>= imm8 -def SHRmi8 : I2A8 <"shr", 0xC0, MRM5m >; // [mem8] >>= imm8 -def SHRmi16 : I2A8 <"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm8 -def SHRmi32 : I2A8 <"shr", 0xC1, MRM5m >; // [mem32] >>= imm8 +// def SHRmi8 : I2A8 <"shr", 0xC0, MRM5m >; // [mem8] >>= imm8 +// def SHRmi16 : I2A8 <"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm8 +// def SHRmi32 : I2A8 <"shr", 0xC1, MRM5m >; // [mem32] >>= imm8 def SARrCL8 : I2A8 <"sar", 0xD2, MRM7r > , UsesCL; // R8 >>>= cl def SARrCL16 : I2A16<"sar", 0xD3, MRM7r >, OpSize, UsesCL; // R16 >>>= cl @@ -492,19 +492,19 @@ def SARmCL32 : I2A32<"sar", 0xD3, MRM7m > , UsesCL; // [mem32] >>>= c def SARri8 : I2A8 <"sar", 0xC0, MRM7r >; // R8 >>>= imm8 def SARri16 : I2A8 <"sar", 0xC1, MRM7r >, OpSize; // R16 >>>= imm8 def SARri32 : I2A8 <"sar", 0xC1, MRM7r >; // R32 >>>= imm8 -def SARmi8 : I2A8 <"sar", 0xC0, MRM7m >; // [mem8] >>>= imm8 -def SARmi16 : I2A8 <"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm8 -def SARmi32 : I2A8 <"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8 +// def SARmi8 : I2A8 <"sar", 0xC0, MRM7m >; // [mem8] >>>= imm8 +// def SARmi16 : I2A8 <"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm8 +// def SARmi32 : I2A8 <"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8 def SHLDrrCL32 : I2A32<"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl def SHLDmrCL32 : I2A32<"shld", 0xA5, MRMDestMem>, TB, UsesCL; // [mem32] <<= [mem32],R32 cl def SHLDrri32 : I2A8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8 -def SHLDmri32 : I2A8 <"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8 +// def SHLDmri32 : I2A8 <"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8 def SHRDrrCL32 : I2A32<"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl def SHRDmrCL32 : I2A32<"shrd", 0xAD, MRMDestMem>, TB, UsesCL; // [mem32] >>= [mem32],R32 cl def SHRDrri32 : I2A8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8 -def SHRDmri32 : I2A8 <"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8 +// def SHRDmri32 : I2A8 <"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8 // Condition code ops, incl. set if equal/not equal/... def SAHF : X86Inst<"sahf" , 0x9E, RawFrm, Arg8>, Imp<[AH],[]>; // flags = AH diff --git a/lib/Target/X86/X86PeepholeOpt.cpp b/lib/Target/X86/X86PeepholeOpt.cpp index 1640862270b..b27602af48a 100644 --- a/lib/Target/X86/X86PeepholeOpt.cpp +++ b/lib/Target/X86/X86PeepholeOpt.cpp @@ -156,7 +156,10 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB, } return false; - +// FIXME: The printer currently does not play well with instructions +// that have immediates and memory operands with size mismatches so +// the following are disabled. +#if 0 case X86::ADDmi16: case X86::ADDmi32: case X86::SUBmi16: case X86::SUBmi32: case X86::ANDmi16: case X86::ANDmi32: @@ -192,6 +195,7 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB, } } return false; +#endif #if 0 case X86::MOVri32: Size++; diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index e288f42074b..a09f87ab0bc 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -207,25 +207,25 @@ bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI, case X86::SHLrCL8: NI = MakeMInst( X86::SHLmCL8 ,FrameIndex, MI); break; case X86::SHLrCL16:NI = MakeMInst( X86::SHLmCL16,FrameIndex, MI); break; case X86::SHLrCL32:NI = MakeMInst( X86::SHLmCL32,FrameIndex, MI); break; - case X86::SHLri8: NI = MakeMIInst(X86::SHLmi8 , FrameIndex, MI); break; - case X86::SHLri16: NI = MakeMIInst(X86::SHLmi16, FrameIndex, MI); break; - case X86::SHLri32: NI = MakeMIInst(X86::SHLmi32, FrameIndex, MI); break; +// case X86::SHLri8: NI = MakeMIInst(X86::SHLmi8 , FrameIndex, MI); break; +// case X86::SHLri16: NI = MakeMIInst(X86::SHLmi16, FrameIndex, MI); break; +// case X86::SHLri32: NI = MakeMIInst(X86::SHLmi32, FrameIndex, MI); break; case X86::SHRrCL8: NI = MakeMInst( X86::SHRmCL8 ,FrameIndex, MI); break; case X86::SHRrCL16:NI = MakeMInst( X86::SHRmCL16,FrameIndex, MI); break; case X86::SHRrCL32:NI = MakeMInst( X86::SHRmCL32,FrameIndex, MI); break; - case X86::SHRri8: NI = MakeMIInst(X86::SHRmi8 , FrameIndex, MI); break; - case X86::SHRri16: NI = MakeMIInst(X86::SHRmi16, FrameIndex, MI); break; - case X86::SHRri32: NI = MakeMIInst(X86::SHRmi32, FrameIndex, MI); break; +// case X86::SHRri8: NI = MakeMIInst(X86::SHRmi8 , FrameIndex, MI); break; +// case X86::SHRri16: NI = MakeMIInst(X86::SHRmi16, FrameIndex, MI); break; +// case X86::SHRri32: NI = MakeMIInst(X86::SHRmi32, FrameIndex, MI); break; case X86::SARrCL8: NI = MakeMInst( X86::SARmCL8 ,FrameIndex, MI); break; case X86::SARrCL16:NI = MakeMInst( X86::SARmCL16,FrameIndex, MI); break; case X86::SARrCL32:NI = MakeMInst( X86::SARmCL32,FrameIndex, MI); break; - case X86::SARri8: NI = MakeMIInst(X86::SARmi8 , FrameIndex, MI); break; - case X86::SARri16: NI = MakeMIInst(X86::SARmi16, FrameIndex, MI); break; - case X86::SARri32: NI = MakeMIInst(X86::SARmi32, FrameIndex, MI); break; +// case X86::SARri8: NI = MakeMIInst(X86::SARmi8 , FrameIndex, MI); break; +// case X86::SARri16: NI = MakeMIInst(X86::SARmi16, FrameIndex, MI); break; +// case X86::SARri32: NI = MakeMIInst(X86::SARmi32, FrameIndex, MI); break; case X86::SHLDrrCL32:NI = MakeMRInst( X86::SHLDmrCL32,FrameIndex, MI);break; - case X86::SHLDrri32: NI = MakeMRIInst(X86::SHLDmri32, FrameIndex, MI);break; +// case X86::SHLDrri32: NI = MakeMRIInst(X86::SHLDmri32, FrameIndex, MI);break; case X86::SHRDrrCL32:NI = MakeMRInst( X86::SHRDmrCL32,FrameIndex, MI);break; - case X86::SHRDrri32: NI = MakeMRIInst(X86::SHRDmri32, FrameIndex, MI);break; +// case X86::SHRDrri32: NI = MakeMRIInst(X86::SHRDmri32, FrameIndex, MI);break; case X86::SETBr: NI = MakeMInst( X86::SETBm, FrameIndex, MI); break; case X86::SETAEr: NI = MakeMInst( X86::SETAEm, FrameIndex, MI); break; case X86::SETEr: NI = MakeMInst( X86::SETEm, FrameIndex, MI); break; -- 2.11.0