From 757642511dffd05af54f262acc8a04a31f4773eb Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 1 Sep 2017 18:38:02 +0000 Subject: [PATCH] AMDGPU: Add ds_{read|write}_addtid_b32 definitions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312349 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPU.td | 3 +++ lib/Target/AMDGPU/DSInstructions.td | 10 ++++++++++ test/MC/AMDGPU/ds-gfx9.s | 8 ++++++++ 3 files changed, 21 insertions(+) diff --git a/lib/Target/AMDGPU/AMDGPU.td b/lib/Target/AMDGPU/AMDGPU.td index 4e20b44dc34..20eb8100f1a 100644 --- a/lib/Target/AMDGPU/AMDGPU.td +++ b/lib/Target/AMDGPU/AMDGPU.td @@ -695,6 +695,9 @@ def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">, def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">, AssemblerPredicate<"FeatureGFX9Insts">; +def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">, + AssemblerPredicate<"FeatureGFX9Insts">; + def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">, AssemblerPredicate<"FeatureAddNoCarryInsts">; diff --git a/lib/Target/AMDGPU/DSInstructions.td b/lib/Target/AMDGPU/DSInstructions.td index e12a892a145..fb72e5178b5 100644 --- a/lib/Target/AMDGPU/DSInstructions.td +++ b/lib/Target/AMDGPU/DSInstructions.td @@ -291,6 +291,10 @@ def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<"ds_write_b8_d16_hi">; def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">; } +let SubtargetPredicate = HasDSAddTid in { +def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">; +} + } def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">; @@ -471,6 +475,10 @@ def DS_READ_I8_D16_HI : DS_1A_RET<"ds_read_i8_d16_hi">; def DS_READ_U16_D16 : DS_1A_RET<"ds_read_u16_d16">; def DS_READ_U16_D16_HI : DS_1A_RET<"ds_read_u16_d16_hi">; } + +let SubtargetPredicate = HasDSAddTid in { +def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">; +} } def DS_CONSUME : DS_0A_RET<"ds_consume">; @@ -849,6 +857,7 @@ def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>; def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>; def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>; def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>; +def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>; def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>; def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>; def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>; @@ -880,6 +889,7 @@ def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>; def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>; def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>; def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>; +def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>; def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>; def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>; def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>; diff --git a/test/MC/AMDGPU/ds-gfx9.s b/test/MC/AMDGPU/ds-gfx9.s index fd9d193da21..7c67a3f7edd 100644 --- a/test/MC/AMDGPU/ds-gfx9.s +++ b/test/MC/AMDGPU/ds-gfx9.s @@ -32,3 +32,11 @@ ds_write_b8_d16_hi v8, v2 ds_write_b16_d16_hi v8, v2 // VI-ERR: error: instruction not supported on this GPU // GFX9: ds_write_b16_d16_hi v8, v2 ; encoding: [0x00,0x00,0xaa,0xd8,0x08,0x02,0x00,0x00] + +ds_write_addtid_b32 v8, v2 +// VI-ERR: error: instruction not supported on this GPU +// GFX9: ds_write_addtid_b32 v8, v2 ; encoding: [0x00,0x00,0x3a,0xd8,0x08,0x02,0x00,0x00] + +ds_read_addtid_b32 v8, v2 +// VI-ERR: error: instruction not supported on this GPU +// GFX9: ds_read_addtid_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd9,0x02,0x00,0x00,0x08] -- 2.11.0