From 75bff895e450f7b4fd17196cbcdac0a960a4e658 Mon Sep 17 00:00:00 2001 From: Venkatraman Govindaraju Date: Sun, 2 Mar 2014 22:55:53 +0000 Subject: [PATCH] [Sparc] Add return/rett instruction to Sparc backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202666 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 6 +++++ .../Sparc/Disassembler/SparcDisassembler.cpp | 30 ++++++++++++++++++++++ lib/Target/Sparc/SparcInstrAliases.td | 2 ++ lib/Target/Sparc/SparcInstrInfo.td | 8 ++++++ test/MC/Disassembler/Sparc/sparc.txt | 3 +++ test/MC/Sparc/sparc-ctrl-instructions.s | 2 ++ test/MC/Sparc/sparc64-ctrl-instructions.s | 3 +++ 7 files changed, 54 insertions(+) diff --git a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 901560c5c97..2ff6cdd8f43 100644 --- a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -446,6 +446,9 @@ ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) return Error(StartLoc, "invalid register name"); } +static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features, + unsigned VariantID); + bool SparcAsmParser:: ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, @@ -455,6 +458,9 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef Name, // First operand in MCInst is instruction mnemonic. Operands.push_back(SparcOperand::CreateToken(Name, NameLoc)); + // apply mnemonic aliases, if any, so that we can parse operands correctly. + applyMnemonicAliases(Name, getAvailableFeatures(), 0); + if (getLexer().isNot(AsmToken::EndOfStatement)) { // Read the first operand. if (getLexer().is(AsmToken::Comma)) { diff --git a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp index ea4d6da3ebe..df2d3798a24 100644 --- a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -209,6 +209,8 @@ static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, + const void *Decoder); #include "SparcGenDisassemblerTables.inc" @@ -415,3 +417,31 @@ static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address, } return MCDisassembler::Success; } + +static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, + const void *Decoder) { + + unsigned rs1 = fieldFromInstruction(insn, 14, 5); + unsigned isImm = fieldFromInstruction(insn, 13, 1); + unsigned rs2 = 0; + unsigned simm13 = 0; + if (isImm) + simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); + else + rs2 = fieldFromInstruction(insn, 0, 5); + + // Decode RS1. + DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + + // Decode RS2 | SIMM13. + if (isImm) + MI.addOperand(MCOperand::CreateImm(simm13)); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + } + return MCDisassembler::Success; +} diff --git a/lib/Target/Sparc/SparcInstrAliases.td b/lib/Target/Sparc/SparcInstrAliases.td index a77f248e43e..974fa849f22 100644 --- a/lib/Target/Sparc/SparcInstrAliases.td +++ b/lib/Target/Sparc/SparcInstrAliases.td @@ -249,6 +249,8 @@ def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; // restore -> restore %g0, %g0, %g0 def : InstAlias<"restore", (RESTORErr G0, G0, G0)>; +def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>; + def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>; def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>; diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 11e3c7467dd..9de8f3790d5 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -406,6 +406,14 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, "jmp %i7+$val", []>; } +let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, + isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in { + def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr), + "rett $addr", []>; + def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr), + "rett $addr", []>; +} + // Section B.1 - Load Integer Instructions, p. 90 let DecoderMethod = "DecodeLoadInt" in { defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>; diff --git a/test/MC/Disassembler/Sparc/sparc.txt b/test/MC/Disassembler/Sparc/sparc.txt index 289c738800f..a9420246361 100644 --- a/test/MC/Disassembler/Sparc/sparc.txt +++ b/test/MC/Disassembler/Sparc/sparc.txt @@ -197,3 +197,6 @@ # CHECK: ret 0x81,0xc7,0xe0,0x08 + +# CHECK: rett %i7+8 +0x81 0xcf 0xe0 0x08 diff --git a/test/MC/Sparc/sparc-ctrl-instructions.s b/test/MC/Sparc/sparc-ctrl-instructions.s index ac4ead1ee04..cf92e7045d4 100644 --- a/test/MC/Sparc/sparc-ctrl-instructions.s +++ b/test/MC/Sparc/sparc-ctrl-instructions.s @@ -274,3 +274,5 @@ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 fbo,a .BB0 + ! CHECK: rett %i7+8 ! encoding: [0x81,0xcf,0xe0,0x08] + rett %i7 + 8 diff --git a/test/MC/Sparc/sparc64-ctrl-instructions.s b/test/MC/Sparc/sparc64-ctrl-instructions.s index d3f633daf3f..1484e0c84c1 100644 --- a/test/MC/Sparc/sparc64-ctrl-instructions.s +++ b/test/MC/Sparc/sparc64-ctrl-instructions.s @@ -1214,3 +1214,6 @@ fmovrsnz %g1, %f2, %f3 fmovrsgz %g1, %f2, %f3 fmovrsgez %g1, %f2, %f3 + + ! CHECK: rett %i7+8 ! encoding: [0x81,0xcf,0xe0,0x08] + return %i7 + 8 -- 2.11.0