From 7710e2553b7c2907005b3372315ffc11b1b11aed Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Wed, 29 Oct 2014 15:23:11 +0000 Subject: [PATCH] Whitespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220857 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/CodeGenPrepare.cpp | 4 +- lib/CodeGen/PostRASchedulerList.cpp | 10 ++--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 52 +++++++++++------------ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 2 +- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 12 +++--- 5 files changed, 40 insertions(+), 40 deletions(-) diff --git a/lib/CodeGen/CodeGenPrepare.cpp b/lib/CodeGen/CodeGenPrepare.cpp index 2e2eabd8f1e..ffff18c9ae0 100644 --- a/lib/CodeGen/CodeGenPrepare.cpp +++ b/lib/CodeGen/CodeGenPrepare.cpp @@ -2759,8 +2759,8 @@ bool CodeGenPrepare::OptimizeMemoryInst(Instruction *MemoryInst, Value *Addr, if (AddrMode.BaseOffs) { Value *V = ConstantInt::get(IntPtrTy, AddrMode.BaseOffs); if (ResultIndex) { - // We need to add this separately from the scale above to help with - // SDAG consecutive load/store merging. + // We need to add this separately from the scale above to help with + // SDAG consecutive load/store merging. if (ResultPtr->getType() != I8PtrTy) ResultPtr = Builder.CreateBitCast(ResultPtr, I8PtrTy); ResultPtr = Builder.CreateGEP(ResultPtr, ResultIndex, "sunkaddr"); diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index 085c4399035..89e1d113ff7 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -97,7 +97,7 @@ namespace { } bool runOnMachineFunction(MachineFunction &Fn) override; - + bool enablePostRAScheduler( const TargetSubtargetInfo &ST, CodeGenOpt::Level OptLevel, TargetSubtargetInfo::AntiDepBreakMode &Mode, @@ -559,10 +559,10 @@ void SchedulePostRATDList::ListScheduleTopDown() { if (HT == ScheduleHazardRecognizer::NoHazard) { if (HazardRec->ShouldPreferAnother(CurSUnit)) { if (!NotPreferredSUnit) { - // If this is the first non-preferred node for this cycle, then - // record it and continue searching for a preferred node. If this - // is not the first non-preferred node, then treat it as though - // there had been a hazard. + // If this is the first non-preferred node for this cycle, then + // record it and continue searching for a preferred node. If this + // is not the first non-preferred node, then treat it as though + // there had been a hazard. NotPreferredSUnit = CurSUnit; continue; } diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 4ad2e5dd492..acea763f5ba 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4678,7 +4678,7 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) { if (N0.getOpcode() == ISD::SETCC) { if ((!LegalOperations && TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) || - TLI.isOperationLegal(ISD::SELECT_CC, VT)) + TLI.isOperationLegal(ISD::SELECT_CC, VT)) return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, N0.getOperand(0), N0.getOperand(1), N1, N2, N0.getOperand(2)); @@ -6571,7 +6571,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { ConstantFPSDNode *N1CFP = dyn_cast(N1); EVT VT = N->getValueType(0); const TargetOptions &Options = DAG.getTarget().Options; - + // fold vector ops if (VT.isVector()) { SDValue FoldedVOp = SimplifyVBinOp(N); @@ -6591,7 +6591,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { isNegatibleForFree(N1, LegalOperations, TLI, &Options) == 2) return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, GetNegatedExpression(N1, DAG, LegalOperations)); - + // fold (fadd (fneg A), B) -> (fsub B, A) if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && isNegatibleForFree(N0, LegalOperations, TLI, &Options) == 2) @@ -6603,7 +6603,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { // No FP constant should be created after legalization as Instruction // Selection pass has a hard time dealing with FP constants. bool AllowNewConst = (Level < AfterLegalizeDAG); - + // fold (fadd A, 0) -> A if (N1CFP && N1CFP->getValueAPF().isZero()) return N0; @@ -6614,15 +6614,15 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0), DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(1), N1)); - + // If allowed, fold (fadd (fneg x), x) -> 0.0 if (AllowNewConst && N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) return DAG.getConstantFP(0.0, VT); - + // If allowed, fold (fadd x, (fneg x)) -> 0.0 if (AllowNewConst && N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) return DAG.getConstantFP(0.0, VT); - + // We can fold chains of FADD's of the same value into multiplications. // This transform is not safe in general because we are reducing the number // of rounding steps. @@ -6630,7 +6630,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { if (N0.getOpcode() == ISD::FMUL) { ConstantFPSDNode *CFP00 = dyn_cast(N0.getOperand(0)); ConstantFPSDNode *CFP01 = dyn_cast(N0.getOperand(1)); - + // (fadd (fmul x, c), x) -> (fmul x, c+1) if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, @@ -6638,7 +6638,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { DAG.getConstantFP(1.0, VT)); return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, NewCFP); } - + // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2) if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && N1.getOperand(0) == N1.getOperand(1) && @@ -6650,11 +6650,11 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { N0.getOperand(0), NewCFP); } } - + if (N1.getOpcode() == ISD::FMUL) { ConstantFPSDNode *CFP10 = dyn_cast(N1.getOperand(0)); ConstantFPSDNode *CFP11 = dyn_cast(N1.getOperand(1)); - + // (fadd x, (fmul x, c)) -> (fmul x, c+1) if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, @@ -6682,7 +6682,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, DAG.getConstantFP(3.0, VT)); } - + if (N1.getOpcode() == ISD::FADD && AllowNewConst) { ConstantFPSDNode *CFP10 = dyn_cast(N1.getOperand(0)); // (fadd x, (fadd x, x)) -> (fmul x, 3.0) @@ -6691,7 +6691,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, DAG.getConstantFP(3.0, VT)); } - + // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0) if (AllowNewConst && N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && @@ -6702,7 +6702,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { N0.getOperand(0), DAG.getConstantFP(4.0, VT)); } } // enable-unsafe-fp-math - + // FADD -> FMA combines: if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath) && TLI.isFMAFasterThanFMulAndFAdd(VT) && @@ -7030,7 +7030,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) { return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, DAG.getConstantFP(Recip, VT)); } - + // If this FDIV is part of a reciprocal square root, it may be folded // into a target-specific square root estimate instruction. if (N1.getOpcode() == ISD::FSQRT) { @@ -7073,7 +7073,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) { } } } - + // Fold into a reciprocal estimate and multiply instead of a real divide. if (SDValue RV = BuildReciprocalEstimate(N1)) { AddToWorklist(RV.getNode()); @@ -7548,7 +7548,7 @@ SDValue DAGCombiner::visitFABS(SDNode *N) { // fold (fabs c1) -> fabs(c1) if (isa(N0)) return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); - + // fold (fabs (fabs x)) -> (fabs x) if (N0.getOpcode() == ISD::FABS) return N->getOperand(0); @@ -11070,7 +11070,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { if (isUndefMask) return DAG.getUNDEF(VT); - + bool CommuteOperands = false; if (N0.getOperand(1).getOpcode() != ISD::UNDEF) { // To be valid, the combine shuffle mask should only reference elements @@ -11109,12 +11109,12 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { // The combined shuffle must map each index to itself. IsIdentityMask = (unsigned)Mask[i] == i + BaseMaskIndex; } - + if (IsIdentityMask) { if (CommuteOperands) // optimize shuffle(shuffle(x, y), undef) -> y. return OtherSV->getOperand(1); - + // optimize shuffle(shuffle(x, undef), undef) -> x // optimize shuffle(shuffle(x, y), undef) -> x return OtherSV->getOperand(0); @@ -11993,26 +11993,26 @@ SDValue DAGCombiner::BuildRsqrtNROneConst(SDValue Arg, SDValue Est, EVT VT = Arg.getValueType(); SDLoc DL(Arg); SDValue ThreeHalves = DAG.getConstantFP(1.5, VT); - + // We now need 0.5 * Arg which we can write as (1.5 * Arg - Arg) so that // this entire sequence requires only one FP constant. SDValue HalfArg = DAG.getNode(ISD::FMUL, DL, VT, ThreeHalves, Arg); AddToWorklist(HalfArg.getNode()); - + HalfArg = DAG.getNode(ISD::FSUB, DL, VT, HalfArg, Arg); AddToWorklist(HalfArg.getNode()); - + // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est) for (unsigned i = 0; i < Iterations; ++i) { SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, Est); AddToWorklist(NewEst.getNode()); - + NewEst = DAG.getNode(ISD::FMUL, DL, VT, HalfArg, NewEst); AddToWorklist(NewEst.getNode()); - + NewEst = DAG.getNode(ISD::FSUB, DL, VT, ThreeHalves, NewEst); AddToWorklist(NewEst.getNode()); - + Est = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst); AddToWorklist(Est.getNode()); } diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 6b00bb10824..b73bb0a897b 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -965,7 +965,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { EVT VecVT = N->getValueType(0); unsigned NumElts = VecVT.getVectorNumElements(); assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) && - "Legal vector of one illegal element?"); + "Legal vector of one illegal element?"); // Promote the inserted value. The type does not need to match the // vector element type. Check that any extra bits introduced will be diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index db03e2ad8fd..4fbe672f3e7 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2703,7 +2703,7 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector *Created) const { assert(Created && "No vector to hold udiv ops."); - + EVT VT = N->getValueType(0); SDLoc dl(N); @@ -2780,7 +2780,7 @@ verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const { bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL, SDValue LH, - SDValue RL, SDValue RH) const { + SDValue RL, SDValue RH) const { EVT VT = N->getValueType(0); SDLoc dl(N); @@ -2813,8 +2813,8 @@ bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, // The inputs are both zero-extended. if (HasUMUL_LOHI) { // We can emit a umul_lohi. - Lo = DAG.getNode(ISD::UMUL_LOHI, dl, - DAG.getVTList(HiLoVT, HiLoVT), LL, RL); + Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL, + RL); Hi = SDValue(Lo.getNode(), 1); return true; } @@ -2829,8 +2829,8 @@ bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, // The input values are both sign-extended. if (HasSMUL_LOHI) { // We can emit a smul_lohi. - Lo = DAG.getNode(ISD::SMUL_LOHI, dl, - DAG.getVTList(HiLoVT, HiLoVT), LL, RL); + Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL, + RL); Hi = SDValue(Lo.getNode(), 1); return true; } -- 2.11.0