From 7b9683892c75db3778cadb9fde2e92e7e2887d81 Mon Sep 17 00:00:00 2001 From: Imran Khan Date: Mon, 3 Apr 2017 13:11:18 +0530 Subject: [PATCH] arm64: cache: change ARCH_DMA_MINALIGN and L1_CACHE_SHIFT values This reverts 'commit 97303480753e ("arm64: Increase the max granular size") and also sets ARM_DMA_MINALIGN to 128. ARCH_DMA_MINALIGN is dependent on L1_CACHE_SHIFT but it should be set to maximum *known* cache line size on ARMv8 systems to avoid DMA coherecy issues. So setting ARM_DMA_MINALIGN to 128. Signed-off-by: Catalin Marinas Change-Id: Ie771d1b693789fce8793538a6efddfe68e2a0043 Patch-mainline: linux-kernel @ 21/03/16, 17:14:03 Signed-off-by: Imran Khan --- arch/arm64/include/asm/cache.h | 12 ++++++------ arch/arm64/kernel/cpufeature.c | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 5082b30bc2c0..f9359d32fae5 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -18,17 +18,17 @@ #include -#define L1_CACHE_SHIFT 7 +#define L1_CACHE_SHIFT 6 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /* * Memory returned by kmalloc() may be used for DMA, so we must make - * sure that all such allocations are cache aligned. Otherwise, - * unrelated code may cause parts of the buffer to be read into the - * cache before the transfer is done, causing old data to be seen by - * the CPU. + * sure that all such allocations are aligned to the maximum *known* + * cache line size on ARMv8 systems. Otherwise, unrelated code may + * cause parts of the buffer to be read into the cache before the + * transfer is done, causing old data to be seen by the CPU. */ -#define ARCH_DMA_MINALIGN L1_CACHE_BYTES +#define ARCH_DMA_MINALIGN (128) #ifndef __ASSEMBLY__ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index cdf1dca64133..f75000996e4c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -992,9 +992,9 @@ void __init setup_cpu_features(void) if (!cwg) pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", cls); - if (L1_CACHE_BYTES < cls) - pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", - L1_CACHE_BYTES, cls); + if (ARCH_DMA_MINALIGN < cls) + pr_warn("ARCH_DMA_MINALIGN smaller than the Cache Writeback Granule (%d < %d)\n", + ARCH_DMA_MINALIGN, cls); } static bool __maybe_unused -- 2.11.0