From 7cf693af555e40bf47257bd4276a2048aaaca947 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Thu, 24 Sep 2015 12:10:23 +0000 Subject: [PATCH] [mips] Use PredicateControl for the MSA ASE instructions. NFC. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13092 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248486 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsInstrInfo.td | 11 +++++++++++ lib/Target/Mips/MipsMSAInstrFormats.td | 24 +++++++----------------- lib/Target/Mips/MipsMSAInstrInfo.td | 10 +++++----- 3 files changed, 23 insertions(+), 22 deletions(-) diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index aa77c6d50da..cbc8e2fcb8f 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -208,6 +208,9 @@ def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">; def HasEVA : Predicate<"Subtarget->hasEVA()">, AssemblerPredicate<"FeatureEVA,FeatureMips32r2">; +def HasMSA : Predicate<"Subtarget->hasMSA()">, + AssemblerPredicate<"FeatureMSA">; + //===----------------------------------------------------------------------===// // Mips GPR size adjectives. @@ -300,6 +303,14 @@ class INSN_MIPS5_32R2_NOT_32R6_64R6 { list InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6]; } +class ASE_MSA { + list InsnPredicates = [HasMSA]; +} + +class ASE_MSA64 { + list InsnPredicates = [HasMSA, HasMips64]; +} + // Class used for separating microMIPSr6 and microMIPS (r3) instruction. // It can be used only on instructions that doesn't inherit PredicateControl. class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl { diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td index bff2d0fab1e..7d25ea56e3d 100644 --- a/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/lib/Target/Mips/MipsMSAInstrFormats.td @@ -7,18 +7,12 @@ // //===----------------------------------------------------------------------===// -def HasMSA : Predicate<"Subtarget->hasMSA()">, - AssemblerPredicate<"FeatureMSA">; - -class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { - let Predicates = [HasMSA]; +class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, + PredicateControl, ASE_MSA { + let EncodingPredicates = [HasStdEnc]; let Inst{31-26} = 0b011110; } -class MSA64Inst : MSAInst { - let Predicates = [HasMSA, HasMips64]; -} - class MSACBranch : MSAInst { let Inst{31-26} = 0b010001; } @@ -27,10 +21,6 @@ class MSASpecial : MSAInst { let Inst{31-26} = 0b000000; } -class MSA64Special : MSA64Inst { - let Inst{31-26} = 0b000000; -} - class MSAPseudo pattern, InstrItinClass itin = IIPseudo>: MipsPseudo { @@ -100,7 +90,7 @@ class MSA_2R_FILL_FMT major, bits<2> df, bits<6> minor>: MSAInst { let Inst{5-0} = minor; } -class MSA_2R_FILL_D_FMT major, bits<2> df, bits<6> minor>: MSA64Inst { +class MSA_2R_FILL_D_FMT major, bits<2> df, bits<6> minor>: MSAInst { bits<5> rs; bits<5> wd; @@ -293,7 +283,7 @@ class MSA_ELM_COPY_W_FMT major, bits<6> minor>: MSAInst { let Inst{5-0} = minor; } -class MSA_ELM_COPY_D_FMT major, bits<6> minor>: MSA64Inst { +class MSA_ELM_COPY_D_FMT major, bits<6> minor>: MSAInst { bits<4> n; bits<5> ws; bits<5> rd; @@ -345,7 +335,7 @@ class MSA_ELM_INSERT_W_FMT major, bits<6> minor>: MSAInst { let Inst{5-0} = minor; } -class MSA_ELM_INSERT_D_FMT major, bits<6> minor>: MSA64Inst { +class MSA_ELM_INSERT_D_FMT major, bits<6> minor>: MSAInst { bits<6> n; bits<5> rs; bits<5> wd; @@ -450,7 +440,7 @@ class SPECIAL_LSA_FMT minor>: MSASpecial { let Inst{5-0} = minor; } -class SPECIAL_DLSA_FMT minor>: MSA64Special { +class SPECIAL_DLSA_FMT minor>: MSASpecial { bits<5> rs; bits<5> rt; bits<5> rd; diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 9e348d708b1..df873d92953 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -2991,12 +2991,12 @@ def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC; def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC; def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC; def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC; -def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC; +def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64; def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC; def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC; def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC; -def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC; +def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC, ASE_MSA64; def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC; def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC; @@ -3108,7 +3108,7 @@ def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; def FILL_B : FILL_B_ENC, FILL_B_DESC; def FILL_H : FILL_H_ENC, FILL_H_DESC; def FILL_W : FILL_W_ENC, FILL_W_DESC; -def FILL_D : FILL_D_ENC, FILL_D_DESC; +def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64; def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; @@ -3238,7 +3238,7 @@ def ILVR_D : ILVR_D_ENC, ILVR_D_DESC; def INSERT_B : INSERT_B_ENC, INSERT_B_DESC; def INSERT_H : INSERT_H_ENC, INSERT_H_DESC; def INSERT_W : INSERT_W_ENC, INSERT_W_DESC; -def INSERT_D : INSERT_D_ENC, INSERT_D_DESC; +def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64; // INSERT_FW_PSEUDO defined after INSVE_W // INSERT_FD_PSEUDO defined after INSVE_D @@ -3280,7 +3280,7 @@ def LDI_W : LDI_W_ENC, LDI_W_DESC; def LDI_D : LDI_D_ENC, LDI_D_DESC; def LSA : LSA_ENC, LSA_DESC; -def DLSA : DLSA_ENC, DLSA_DESC; +def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64; def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; -- 2.11.0