From 7cf9cd64e41aade956f3d7fa4a0d7c0ab5bc76bd Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 10 May 2019 22:03:33 +0000 Subject: [PATCH] [X86] Disable speculative load hardening for operations with an explicit RSP base. After D58632, we can create idempotent atomic operations to the top of stack. This confused speculative load hardening because it thinks accesses should have virtual register base except for the cases it already excluded. This commit adds a new exclusion for this case. I'll try to reduce a test case for this, but this fix was verified to work by the reporter. This should avoid needing to revert D58632. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360475 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86SpeculativeLoadHardening.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/lib/Target/X86/X86SpeculativeLoadHardening.cpp index c8b740ca39e..af0c7635a9f 100644 --- a/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -1964,6 +1964,14 @@ void X86SpeculativeLoadHardeningPass::hardenLoadAddr( LLVM_DEBUG( dbgs() << " Skipping hardening base of explicit stack frame load: "; MI.dump(); dbgs() << "\n"); + } else if (BaseMO.getReg() == X86::RSP) { + // Some idempotent atomic operations are lowered directly to a locked + // OR with 0 to the top of stack(or slightly offset from top) which uses an + // explicit RSP register as the base. + assert(IndexMO.getReg() == X86::NoRegister && + "Explicit RSP access with dynamic index!"); + LLVM_DEBUG( + dbgs() << " Cannot harden base of explicit RSP offset in a load!"); } else if (BaseMO.getReg() == X86::RIP || BaseMO.getReg() == X86::NoRegister) { // For both RIP-relative addressed loads or absolute loads, we cannot -- 2.11.0