From 7e169cec74b09dc7a0eeafcb21e9f827314265ef Mon Sep 17 00:00:00 2001 From: Puyan Lotfi Date: Thu, 9 Jul 2020 11:35:00 -0700 Subject: [PATCH] [NFC][test] Adding fastcc test case for promoted 16-bit integer bitcasts. The following: https://reviews.llvm.org/D82552 fixed an assert in the SelectionDag ISel legalizer for some CCs on armv7. I noticed that this fix also fixes the assert when using fastcc, so I am adding a fastcc regression test here. Differential Revision: https://reviews.llvm.org/D82443 --- llvm/test/CodeGen/ARM/arm-half-promote.ll | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/llvm/test/CodeGen/ARM/arm-half-promote.ll b/llvm/test/CodeGen/ARM/arm-half-promote.ll index 1d81273a6fd..f3c9a9e081b 100644 --- a/llvm/test/CodeGen/ARM/arm-half-promote.ll +++ b/llvm/test/CodeGen/ARM/arm-half-promote.ll @@ -51,3 +51,31 @@ define swiftcc { <8 x half>, <8 x half> } @f2() { ; CHECK-NEXT: bx lr ret { <8 x half>, <8 x half> } zeroinitializer } + +define fastcc { <8 x half>, <8 x half> } @f3() { +; CHECK-LABEL: _f3 +; CHECK: vpush {d8} +; CHECK-NEXT: vmov.f64 d8, #5.000000e-01 +; CHECK-NEXT: vmov.i32 d8, #0x0 +; CHECK-NEXT: vmov.i32 d0, #0x0 +; CHECK-NEXT: vmov.i32 d1, #0x0 +; CHECK-NEXT: vmov.i32 d2, #0x0 +; CHECK-NEXT: vmov.i32 d3, #0x0 +; CHECK-NEXT: vmov.i32 d4, #0x0 +; CHECK-NEXT: vmov.i32 d5, #0x0 +; CHECK-NEXT: vmov.i32 d6, #0x0 +; CHECK-NEXT: vmov.i32 d7, #0x0 +; CHECK-NEXT: vmov.f32 s1, s16 +; CHECK-NEXT: vmov.f32 s3, s16 +; CHECK-NEXT: vmov.f32 s5, s16 +; CHECK-NEXT: vmov.f32 s7, s16 +; CHECK-NEXT: vmov.f32 s9, s16 +; CHECK-NEXT: vmov.f32 s11, s16 +; CHECK-NEXT: vmov.f32 s13, s16 +; CHECK-NEXT: vmov.f32 s15, s16 +; CHECK-NEXT: vpop {d8} +; CHECK-NEXT: bx lr + + ret { <8 x half>, <8 x half> } zeroinitializer +} + -- 2.11.0