From 7eaac1c18c01ab6178825864893cd9a7d1376fd5 Mon Sep 17 00:00:00 2001
From: Sam Parker <sam.parker@arm.com>
Date: Fri, 15 Mar 2019 13:36:37 +0000
Subject: [PATCH] [ARM] Remove EarlyCSE from backend

There is an issue with early CSE hitting an assert, so temporarily
remove the pass from the Arm backend.

Bug: https://bugs.llvm.org/show_bug.cgi?id=41081

Differential Revision: https://reviews.llvm.org/D59410


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356259 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMTargetMachine.cpp                |  6 ++----
 test/CodeGen/ARM/O3-pipeline.ll                    |  1 -
 test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll |  8 ++------
 test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll     | 13 +++++++------
 4 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index bd075cda2e4..d0138274d57 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -403,11 +403,9 @@ void ARMPassConfig::addIRPasses() {
 
   TargetPassConfig::addIRPasses();
 
-  // Run the parallel DSP pass and its helpers.
-  if (getOptLevel() == CodeGenOpt::Aggressive) {
-    addPass(createEarlyCSEPass());
+  // Run the parallel DSP pass.
+  if (getOptLevel() == CodeGenOpt::Aggressive) 
     addPass(createARMParallelDSPPass());
-  }
 
   // Match interleaved memory accesses to ldN/stN intrinsics.
   if (TM->getOptLevel() != CodeGenOpt::None)
diff --git a/test/CodeGen/ARM/O3-pipeline.ll b/test/CodeGen/ARM/O3-pipeline.ll
index d9ec9c8e8ea..20bb06ed4be 100644
--- a/test/CodeGen/ARM/O3-pipeline.ll
+++ b/test/CodeGen/ARM/O3-pipeline.ll
@@ -33,7 +33,6 @@
 ; CHECK:      Scalarize Masked Memory Intrinsics
 ; CHECK:      Expand reduction intrinsics
 ; CHECK:      Dominator Tree Construction
-; CHECK:      Early CSE
 ; CHECK:      Natural Loop Information
 ; CHECK:      Scalar Evolution Analysis
 ; CHECK:      Basic Alias Analysis (stateless AA impl)
diff --git a/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll b/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
index 93ac0f5ef2e..03c77eb80dc 100644
--- a/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
+++ b/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
@@ -31,15 +31,11 @@ entry:
   %inc11.us.i.3.i = add i32 %idx, 4
   br label %for.body
 
+; TODO: CSE, or something similar, is required to remove the duplicate loads.
 ; CHECK: %for.body
 ; CHECK: smlad
 ; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
+; CHECK-NOT: smlad r{{.*}}
 
 for.body:
   %A3 = phi i32 [ %add9.us.i.3361.i, %for.body ], [ 0, %entry ]
diff --git a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
index e043773f5cc..34569e9116f 100644
--- a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
+++ b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
@@ -32,12 +32,13 @@
 
 define fastcc i32 @parse_percent_token() nounwind {
 entry:
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
 ; Do not convert into single stream code. BranchProbability Analysis assumes
 ; that branches which goes to "ret" instruction have lower probabilities.
   switch i32 undef, label %bb7 [
-- 
2.11.0