From 7ecda486e97cf17a7d97bbf9e6bfa7e768d51879 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 13 Oct 2018 13:33:32 +0000 Subject: [PATCH] Pull out repeated getOperand(). NFCI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344450 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index bb75f6e0f17..835e272f52b 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -22972,11 +22972,10 @@ static SDValue LowerCTTZ(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG) { MVT VT = Op.getSimpleValueType(); unsigned NumBits = VT.getScalarSizeInBits(); + SDValue N0 = Op.getOperand(0); SDLoc dl(Op); if (VT.isVector()) { - SDValue N0 = Op.getOperand(0); - // Decompose 256-bit ops into smaller 128-bit ops. if (VT.is256BitVector() && !Subtarget.hasInt256()) return Lower256IntUnary(Op, DAG); @@ -23004,7 +23003,7 @@ static SDValue LowerCTTZ(SDValue Op, const X86Subtarget &Subtarget, // Issue a bsf (scan bits forward) which also sets EFLAGS. SDVTList VTs = DAG.getVTList(VT, MVT::i32); - Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0)); + Op = DAG.getNode(X86ISD::BSF, dl, VTs, N0); // If src is zero (i.e. bsf sets ZF), returns NumBits. SDValue Ops[] = { -- 2.11.0