From 7f690e625807b9320bf4ae437b8f35258acc99de Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Thu, 30 Sep 2004 02:15:18 +0000 Subject: [PATCH] Use longer and more explicit names for instance vars (particularly important data structures). Fix the print method to send to the right ostream, not always cerr. Delete typedefs that are only used once. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16606 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/VirtRegMap.cpp | 62 ++++++++++++++++++++++------------------------ lib/CodeGen/VirtRegMap.h | 34 ++++++++++++------------- 2 files changed, 46 insertions(+), 50 deletions(-) diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 52960863712..f6434989a19 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -52,64 +52,62 @@ namespace { //===----------------------------------------------------------------------===// void VirtRegMap::grow() { - v2pMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); - v2ssMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); + Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg()); + Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg()); } int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { assert(MRegisterInfo::isVirtualRegister(virtReg)); - assert(v2ssMap_[virtReg] == NO_STACK_SLOT && + assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && "attempt to assign stack slot to already spilled register"); - const TargetRegisterClass* RC = mf_->getSSARegMap()->getRegClass(virtReg); - int frameIndex = mf_->getFrameInfo()->CreateStackObject(RC->getSize(), - RC->getAlignment()); - v2ssMap_[virtReg] = frameIndex; + const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg); + int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(), + RC->getAlignment()); + Virt2StackSlotMap[virtReg] = frameIndex; ++NumSpills; return frameIndex; } void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { assert(MRegisterInfo::isVirtualRegister(virtReg)); - assert(v2ssMap_[virtReg] == NO_STACK_SLOT && + assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && "attempt to assign stack slot to already spilled register"); - v2ssMap_[virtReg] = frameIndex; + Virt2StackSlotMap[virtReg] = frameIndex; } void VirtRegMap::virtFolded(unsigned virtReg, MachineInstr* oldMI, MachineInstr* newMI) { // move previous memory references folded to new instruction - MI2VirtMap::iterator i, e; - std::vector regs; - for (tie(i, e) = mi2vMap_.equal_range(oldMI); i != e; ) { + MI2VirtMapTy::iterator i, e; + std::vector regs; + for (tie(i, e) = MI2VirtMap.equal_range(oldMI); i != e; ) { regs.push_back(i->second); - mi2vMap_.erase(i++); + MI2VirtMap.erase(i++); } for (unsigned i = 0, e = regs.size(); i != e; ++i) - mi2vMap_.insert(std::make_pair(newMI, i)); + MI2VirtMap.insert(std::make_pair(newMI, i)); // add new memory reference - mi2vMap_.insert(std::make_pair(newMI, virtReg)); + MI2VirtMap.insert(std::make_pair(newMI, virtReg)); } -void VirtRegMap::print(std::ostream& os) const { - const MRegisterInfo* mri = mf_->getTarget().getRegisterInfo(); +void VirtRegMap::print(std::ostream &OS) const { + const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); - std::cerr << "********** REGISTER MAP **********\n"; + OS << "********** REGISTER MAP **********\n"; for (unsigned i = MRegisterInfo::FirstVirtualRegister, - e = mf_->getSSARegMap()->getLastVirtReg(); i <= e; ++i) { - if (v2pMap_[i] != (unsigned)VirtRegMap::NO_PHYS_REG) - std::cerr << "[reg" << i << " -> " - << mri->getName(v2pMap_[i]) << "]\n"; + e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { + if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) + OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; + } for (unsigned i = MRegisterInfo::FirstVirtualRegister, - e = mf_->getSSARegMap()->getLastVirtReg(); i <= e; ++i) { - if (v2ssMap_[i] != VirtRegMap::NO_STACK_SLOT) - std::cerr << "[reg" << i << " -> fi#" - << v2ssMap_[i] << "]\n"; - } - std::cerr << '\n'; + e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) + if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) + OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; + OS << '\n'; } void VirtRegMap::dump() const { print(std::cerr); } @@ -133,7 +131,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF, DEBUG(std::cerr << "********** Function: " << MF.getFunction()->getName() << '\n'); const TargetMachine& TM = MF.getTarget(); - const MRegisterInfo& mri = *TM.getRegisterInfo(); + const MRegisterInfo& MRI = *TM.getRegisterInfo(); DenseMap Loaded; @@ -151,7 +149,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF, unsigned physReg = VRM.getPhys(virtReg); if (mop.isUse() && VRM.hasStackSlot(mop.getReg()) && !Loaded[virtReg]) { - mri.loadRegFromStackSlot(*mbbi, mii, physReg, + MRI.loadRegFromStackSlot(*mbbi, mii, physReg, VRM.getStackSlot(virtReg)); Loaded[virtReg] = true; DEBUG(std::cerr << '\t'; @@ -160,7 +158,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF, } if (mop.isDef() && VRM.hasStackSlot(mop.getReg())) { - mri.storeRegToStackSlot(*mbbi, next(mii), physReg, + MRI.storeRegToStackSlot(*mbbi, next(mii), physReg, VRM.getStackSlot(virtReg)); ++NumStores; } @@ -304,7 +302,7 @@ void LocalSpiller::eliminateVirtRegsInMbb(MachineBasicBlock &MBB) { // if we have references to memory operands make sure // we clear all physical registers that may contain // the value of the spilled virtual register - VirtRegMap::MI2VirtMap::const_iterator i, e; + VirtRegMap::MI2VirtMapTy::const_iterator i, e; for (tie(i, e) = VRM->getFoldedVirts(MI); i != e; ++i) { if (VRM->hasPhys(i->second)) vacateJustPhysReg(MBB, MI, VRM->getPhys(i->second)); diff --git a/lib/CodeGen/VirtRegMap.h b/lib/CodeGen/VirtRegMap.h index 664ca628cf7..b05c6ca5c9c 100644 --- a/lib/CodeGen/VirtRegMap.h +++ b/lib/CodeGen/VirtRegMap.h @@ -26,15 +26,13 @@ namespace llvm { class VirtRegMap { public: - typedef DenseMap Virt2PhysMap; - typedef DenseMap Virt2StackSlotMap; - typedef std::multimap MI2VirtMap; + typedef std::multimap MI2VirtMapTy; private: - MachineFunction* mf_; - Virt2PhysMap v2pMap_; - Virt2StackSlotMap v2ssMap_; - MI2VirtMap mi2vMap_; + MachineFunction &MF; + DenseMap Virt2PhysMap; + DenseMap Virt2StackSlotMap; + MI2VirtMapTy MI2VirtMap; VirtRegMap(const VirtRegMap&); // DO NOT IMPLEMENT void operator=(const VirtRegMap&); // DO NOT IMPLEMENT @@ -45,8 +43,8 @@ namespace llvm { }; public: - VirtRegMap(MachineFunction& mf) - : mf_(&mf), v2pMap_(NO_PHYS_REG), v2ssMap_(NO_STACK_SLOT) { + VirtRegMap(MachineFunction &mf) + : MF(mf), Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) { grow(); } @@ -58,27 +56,27 @@ namespace llvm { unsigned getPhys(unsigned virtReg) const { assert(MRegisterInfo::isVirtualRegister(virtReg)); - return v2pMap_[virtReg]; + return Virt2PhysMap[virtReg]; } void assignVirt2Phys(unsigned virtReg, unsigned physReg) { assert(MRegisterInfo::isVirtualRegister(virtReg) && MRegisterInfo::isPhysicalRegister(physReg)); - assert(v2pMap_[virtReg] == NO_PHYS_REG && + assert(Virt2PhysMap[virtReg] == NO_PHYS_REG && "attempt to assign physical register to already mapped " "virtual register"); - v2pMap_[virtReg] = physReg; + Virt2PhysMap[virtReg] = physReg; } void clearVirt(unsigned virtReg) { assert(MRegisterInfo::isVirtualRegister(virtReg)); - assert(v2pMap_[virtReg] != NO_PHYS_REG && + assert(Virt2PhysMap[virtReg] != NO_PHYS_REG && "attempt to clear a not assigned virtual register"); - v2pMap_[virtReg] = NO_PHYS_REG; + Virt2PhysMap[virtReg] = NO_PHYS_REG; } void clearAllVirt() { - v2pMap_.clear(); + Virt2PhysMap.clear(); grow(); } @@ -88,7 +86,7 @@ namespace llvm { int getStackSlot(unsigned virtReg) const { assert(MRegisterInfo::isVirtualRegister(virtReg)); - return v2ssMap_[virtReg]; + return Virt2StackSlotMap[virtReg]; } int assignVirt2StackSlot(unsigned virtReg); @@ -97,9 +95,9 @@ namespace llvm { void virtFolded(unsigned virtReg, MachineInstr* oldMI, MachineInstr* newMI); - std::pair + std::pair getFoldedVirts(MachineInstr* MI) const { - return mi2vMap_.equal_range(MI); + return MI2VirtMap.equal_range(MI); } void print(std::ostream &OS) const; -- 2.11.0