From 800675f11742b6080e40d17b8d5f35d3a5fc5724 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 3 Nov 2014 18:47:45 +0000 Subject: [PATCH] target-mips: Correct the handling of register #72 on writes Fix an off-by-one error in `mips_cpu_gdb_write_register' for register matching how `mips_cpu_gdb_read_register' handles it. This register slot is a fake anyway, there's nothing in hardware that corresponds to it. Signed-off-by: Maciej W. Rozycki Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- target-mips/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c index f65fec23cc..7e3a604afa 100644 --- a/target-mips/gdbstub.c +++ b/target-mips/gdbstub.c @@ -90,7 +90,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return sizeof(target_ulong); } if (env->CP0_Config1 & (1 << CP0C1_FP) - && n >= 38 && n < 73) { + && n >= 38 && n < 72) { if (n < 70) { if (env->CP0_Status & (1 << CP0St_FR)) { env->active_fpu.fpr[n - 38].d = tmp; -- 2.11.0