From 81d265d692f0043bdbc9eab9cf833ead06a88ad7 Mon Sep 17 00:00:00 2001 From: Nate Begeman Date: Thu, 19 Aug 2004 05:20:54 +0000 Subject: [PATCH] Clean up floating point instruction selection. Change int->float cast code to put conversion constants in constant pool. Shorten code sequence for constant pool fp loads. Remove LOADLoDirect/LOADLoIndirect psuedo instructions and tweak asmwriter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15913 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPC32AsmPrinter.cpp | 25 ++++++++------ lib/Target/PowerPC/PPC32ISelSimple.cpp | 63 ++++++---------------------------- lib/Target/PowerPC/PPC64ISelSimple.cpp | 49 +++----------------------- lib/Target/PowerPC/PPCAsmPrinter.cpp | 25 ++++++++------ lib/Target/PowerPC/PPCInstrInfo.td | 3 +- 5 files changed, 44 insertions(+), 121 deletions(-) diff --git a/lib/Target/PowerPC/PPC32AsmPrinter.cpp b/lib/Target/PowerPC/PPC32AsmPrinter.cpp index 07aaa49be59..1d31e3b1302 100644 --- a/lib/Target/PowerPC/PPC32AsmPrinter.cpp +++ b/lib/Target/PowerPC/PPC32AsmPrinter.cpp @@ -289,6 +289,7 @@ void PPC32AsmPrinter::printMachineInstruction(const MachineInstr *MI) { std::cerr << "Error: untranslated conditional branch psuedo instruction!\n"; abort(); } else if (Opcode == PPC::IMPLICIT_DEF) { + --EmittedInsts; // Not an actual machine instruction O << "; IMPLICIT DEF "; printOp(MI->getOperand(0)); O << "\n"; @@ -306,6 +307,7 @@ void PPC32AsmPrinter::printMachineInstruction(const MachineInstr *MI) { O << "\n"; return; } else if (Opcode == PPC::MovePCtoLR) { + ++EmittedInsts; // Actually two machine instructions // FIXME: should probably be converted to cout.width and cout.fill O << "bl \"L0000" << LabelNumber << "$pb\"\n"; O << "\"L0000" << LabelNumber << "$pb\":\n"; @@ -316,27 +318,28 @@ void PPC32AsmPrinter::printMachineInstruction(const MachineInstr *MI) { } O << TII.getName(Opcode) << " "; - if (Opcode == PPC::LOADLoDirect || Opcode == PPC::LOADLoIndirect) { + if (Opcode == PPC::LOADHiAddr) { printOp(MI->getOperand(0)); - O << ", lo16("; - printOp(MI->getOperand(2), true /* LoadAddrOp */); - O << "-\"L0000" << LabelNumber << "$pb\")"; - O << "("; + O << ", "; if (MI->getOperand(1).getReg() == PPC::R0) O << "0"; else printOp(MI->getOperand(1)); - O << ")\n"; - } else if (Opcode == PPC::LOADHiAddr) { + O << ", ha16(" ; + printOp(MI->getOperand(2), true /* LoadAddrOp */); + O << "-\"L0000" << LabelNumber << "$pb\")\n"; + } else if (ArgCount == 3 && (MI->getOperand(2).isConstantPoolIndex() + || MI->getOperand(2).isGlobalAddress())) { printOp(MI->getOperand(0)); - O << ", "; + O << ", lo16("; + printOp(MI->getOperand(2), true /* LoadAddrOp */); + O << "-\"L0000" << LabelNumber << "$pb\")"; + O << "("; if (MI->getOperand(1).getReg() == PPC::R0) O << "0"; else printOp(MI->getOperand(1)); - O << ", ha16(" ; - printOp(MI->getOperand(2), true /* LoadAddrOp */); - O << "-\"L0000" << LabelNumber << "$pb\")\n"; + O << ")\n"; } else if (ArgCount == 3 && ArgType[1] == PPCII::Disimm16) { printOp(MI->getOperand(0)); O << ", "; diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp index d4d658b58e9..f3eec4a8686 100644 --- a/lib/Target/PowerPC/PPC32ISelSimple.cpp +++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp @@ -617,15 +617,12 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB, // Load addr of constant to reg; constant is located at base + distance unsigned GlobalBase = makeAnotherReg(Type::IntTy); unsigned Reg1 = makeAnotherReg(Type::IntTy); - unsigned Reg2 = makeAnotherReg(Type::IntTy); unsigned Opcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD; // Move value at base + distance into return reg copyGlobalBaseToRegister(MBB, IP, GlobalBase); BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, Reg1).addReg(GlobalBase) .addConstantPoolIndex(CPI); - BuildMI(*MBB, IP, PPC::LOADLoDirect, 2, Reg2).addReg(Reg1) - .addConstantPoolIndex(CPI); - BuildMI(*MBB, IP, Opcode, 2, R).addSImm(0).addReg(Reg2); + BuildMI(*MBB, IP, Opcode, 2, R).addReg(Reg1).addConstantPoolIndex(CPI); } else if (isa(C)) { // Copy zero (null pointer) to the register. BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0); @@ -633,9 +630,9 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB, // GV is located at base + distance unsigned GlobalBase = makeAnotherReg(Type::IntTy); unsigned TmpReg = makeAnotherReg(GV->getType()); - unsigned Opcode = (GV->hasWeakLinkage() || GV->isExternal() - || dyn_cast(GV)) ? - PPC::LOADLoIndirect : PPC::LOADLoDirect; + unsigned Opcode = (GV->hasWeakLinkage() + || GV->isExternal() + || dyn_cast(GV)) ? PPC::LWZ : PPC::LA; // Move value at base + distance into return reg copyGlobalBaseToRegister(MBB, IP, GlobalBase); @@ -1817,21 +1814,6 @@ void ISel::emitBinaryFPOperation(MachineBasicBlock *BB, { PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV }, // Double }; - // Special case: op Reg, - if (ConstantFP *Op1C = dyn_cast(Op1)) { - // Create a constant pool entry for this constant. - MachineConstantPool *CP = F->getConstantPool(); - unsigned CPI = CP->getConstantPoolIndex(Op1C); - const Type *Ty = Op1->getType(); - assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!"); - - unsigned Opcode = OpcodeTab[Ty == Type::DoubleTy][OperatorClass]; - unsigned Op0Reg = getReg(Op0, BB, IP); - unsigned Op1Reg = getReg(Op1C, BB, IP); - BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); - return; - } - // Special case: R1 = op , R2 if (ConstantFP *Op0C = dyn_cast(Op0)) if (Op0C->isExactlyValue(-0.0) && OperatorClass == 1) { @@ -1839,21 +1821,9 @@ void ISel::emitBinaryFPOperation(MachineBasicBlock *BB, unsigned op1Reg = getReg(Op1, BB, IP); BuildMI(*BB, IP, PPC::FNEG, 1, DestReg).addReg(op1Reg); return; - } else { - // Create a constant pool entry for this constant. - MachineConstantPool *CP = F->getConstantPool(); - unsigned CPI = CP->getConstantPoolIndex(Op0C); - const Type *Ty = Op0C->getType(); - assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!"); - - unsigned Opcode = OpcodeTab[Ty == Type::DoubleTy][OperatorClass]; - unsigned Op0Reg = getReg(Op0C, BB, IP); - unsigned Op1Reg = getReg(Op1, BB, IP); - BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); - return; } - unsigned Opcode = OpcodeTab[Op0->getType() != Type::FloatTy][OperatorClass]; + unsigned Opcode = OpcodeTab[Op0->getType() == Type::DoubleTy][OperatorClass]; unsigned Op0r = getReg(Op0, BB, IP); unsigned Op1r = getReg(Op1, BB, IP); BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r); @@ -2706,46 +2676,33 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB, // Spill the integer to memory and reload it from there. // Also spill room for a special conversion constant - int ConstantFrameIndex = - F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData()); int ValueFrameIdx = F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData()); + MachineConstantPool *CP = F->getConstantPool(); unsigned constantHi = makeAnotherReg(Type::IntTy); - unsigned constantLo = makeAnotherReg(Type::IntTy); - unsigned ConstF = makeAnotherReg(Type::DoubleTy); unsigned TempF = makeAnotherReg(Type::DoubleTy); if (!SrcTy->isSigned()) { + ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000000p52); + unsigned ConstF = getReg(CFP, BB, IP); BuildMI(*BB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330); - BuildMI(*BB, IP, PPC::LI, 1, constantLo).addSImm(0); - addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi), - ConstantFrameIndex); - addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantLo), - ConstantFrameIndex, 4); addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi), ValueFrameIdx); addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(SrcReg), ValueFrameIdx, 4); - addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, ConstF), - ConstantFrameIndex); addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, TempF), ValueFrameIdx); BuildMI(*BB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF); } else { + ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000008p52); + unsigned ConstF = getReg(CFP, BB, IP); unsigned TempLo = makeAnotherReg(Type::IntTy); BuildMI(*BB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330); - BuildMI(*BB, IP, PPC::LIS, 1, constantLo).addSImm(0x8000); - addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi), - ConstantFrameIndex); - addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantLo), - ConstantFrameIndex, 4); addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi), ValueFrameIdx); BuildMI(*BB, IP, PPC::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000); addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(TempLo), ValueFrameIdx, 4); - addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, ConstF), - ConstantFrameIndex); addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, TempF), ValueFrameIdx); BuildMI(*BB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF); } diff --git a/lib/Target/PowerPC/PPC64ISelSimple.cpp b/lib/Target/PowerPC/PPC64ISelSimple.cpp index 64f8e5c006e..05de4fbe45e 100644 --- a/lib/Target/PowerPC/PPC64ISelSimple.cpp +++ b/lib/Target/PowerPC/PPC64ISelSimple.cpp @@ -1671,26 +1671,11 @@ void ISel::emitBinaryFPOperation(MachineBasicBlock *BB, Value *Op0, Value *Op1, unsigned OperatorClass, unsigned DestReg) { - // Special case: op Reg, - if (ConstantFP *Op1C = dyn_cast(Op1)) { - // Create a constant pool entry for this constant. - MachineConstantPool *CP = F->getConstantPool(); - unsigned CPI = CP->getConstantPoolIndex(Op1C); - const Type *Ty = Op1->getType(); - assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!"); - - static const unsigned OpcodeTab[][4] = { - { PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS }, // Float - { PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV }, // Double - }; + static const unsigned OpcodeTab[][4] = { + { PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS }, // Float + { PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV }, // Double + }; - unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass]; - unsigned Op1Reg = getReg(Op1C, BB, IP); - unsigned Op0r = getReg(Op0, BB, IP); - BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1Reg); - return; - } - // Special case: R1 = op , R2 if (ConstantFP *Op0C = dyn_cast(Op0)) if (Op0C->isExactlyValue(-0.0) && OperatorClass == 1) { @@ -1698,33 +1683,9 @@ void ISel::emitBinaryFPOperation(MachineBasicBlock *BB, unsigned op1Reg = getReg(Op1, BB, IP); BuildMI(*BB, IP, PPC::FNEG, 1, DestReg).addReg(op1Reg); return; - } else { - // R1 = op CST, R2 --> R1 = opr R2, CST - - // Create a constant pool entry for this constant. - MachineConstantPool *CP = F->getConstantPool(); - unsigned CPI = CP->getConstantPoolIndex(Op0C); - const Type *Ty = Op0C->getType(); - assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!"); - - static const unsigned OpcodeTab[][4] = { - { PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS }, // Float - { PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV }, // Double - }; - - unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass]; - unsigned Op0Reg = getReg(Op0C, BB, IP); - unsigned Op1Reg = getReg(Op1, BB, IP); - BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); - return; } - // General case. - static const unsigned OpcodeTab[] = { - PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV - }; - - unsigned Opcode = OpcodeTab[OperatorClass]; + unsigned Opcode = OpcodeTab[Op0->getType() == Type::DoubleTy][OperatorClass]; unsigned Op0r = getReg(Op0, BB, IP); unsigned Op1r = getReg(Op1, BB, IP); BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r); diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp index 07aaa49be59..1d31e3b1302 100644 --- a/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -289,6 +289,7 @@ void PPC32AsmPrinter::printMachineInstruction(const MachineInstr *MI) { std::cerr << "Error: untranslated conditional branch psuedo instruction!\n"; abort(); } else if (Opcode == PPC::IMPLICIT_DEF) { + --EmittedInsts; // Not an actual machine instruction O << "; IMPLICIT DEF "; printOp(MI->getOperand(0)); O << "\n"; @@ -306,6 +307,7 @@ void PPC32AsmPrinter::printMachineInstruction(const MachineInstr *MI) { O << "\n"; return; } else if (Opcode == PPC::MovePCtoLR) { + ++EmittedInsts; // Actually two machine instructions // FIXME: should probably be converted to cout.width and cout.fill O << "bl \"L0000" << LabelNumber << "$pb\"\n"; O << "\"L0000" << LabelNumber << "$pb\":\n"; @@ -316,27 +318,28 @@ void PPC32AsmPrinter::printMachineInstruction(const MachineInstr *MI) { } O << TII.getName(Opcode) << " "; - if (Opcode == PPC::LOADLoDirect || Opcode == PPC::LOADLoIndirect) { + if (Opcode == PPC::LOADHiAddr) { printOp(MI->getOperand(0)); - O << ", lo16("; - printOp(MI->getOperand(2), true /* LoadAddrOp */); - O << "-\"L0000" << LabelNumber << "$pb\")"; - O << "("; + O << ", "; if (MI->getOperand(1).getReg() == PPC::R0) O << "0"; else printOp(MI->getOperand(1)); - O << ")\n"; - } else if (Opcode == PPC::LOADHiAddr) { + O << ", ha16(" ; + printOp(MI->getOperand(2), true /* LoadAddrOp */); + O << "-\"L0000" << LabelNumber << "$pb\")\n"; + } else if (ArgCount == 3 && (MI->getOperand(2).isConstantPoolIndex() + || MI->getOperand(2).isGlobalAddress())) { printOp(MI->getOperand(0)); - O << ", "; + O << ", lo16("; + printOp(MI->getOperand(2), true /* LoadAddrOp */); + O << "-\"L0000" << LabelNumber << "$pb\")"; + O << "("; if (MI->getOperand(1).getReg() == PPC::R0) O << "0"; else printOp(MI->getOperand(1)); - O << ", ha16(" ; - printOp(MI->getOperand(2), true /* LoadAddrOp */); - O << "-\"L0000" << LabelNumber << "$pb\")\n"; + O << ")\n"; } else if (ArgCount == 3 && ArgType[1] == PPCII::Disimm16) { printOp(MI->getOperand(0)); O << ", "; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 3631ef6d62e..ec1f7a5fc57 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -35,8 +35,7 @@ let Defs = [LR] in def MovePCtoLR : Pseudo<"MovePCtoLR">; def IMPLICIT_DEF : Pseudo<"IMPLICIT_DEF">; -def LOADLoIndirect : DForm_2_r0 <"lwz", 14, 0, 0>; -def LOADLoDirect : DForm_2_r0<"la", 14, 0, 0>; +def LA : DForm_2<"la", 14, 0, 0>; def LOADHiAddr : DForm_2_r0<"addis", 15, 0, 0>; def ADDI : DForm_2<"addi", 14, 0, 0>; -- 2.11.0