From 82eec824a7a9ce9595eea6704ae339d1bdd71dcb Mon Sep 17 00:00:00 2001 From: Ranjeet Singh Date: Fri, 3 Mar 2017 11:40:07 +0000 Subject: [PATCH] [ARM] fpscr read/write intrinsics not aware of each other The intrinsics __builtin_arm_get_fpscr and __builtin_arm_set_fpscr read and write to the fpscr (Floating-Point Status and Control Register) register. A bug exists in the __builtin_arm_get_fpscr intrinsic definition in llvm which treats this intrinsic as a IntroNoMem which means it's not a memory access and doesn't have any other side-effects. Having this property on this intrinsic means that various optimizations can be done on this such as common sub-expression elimination with other reads. This can cause issues if there has been write to this register, e.g. void foo(int *p) { p[0] = __builtin_arm_get_fpscr(); __builtin_arm_set_fpscr(1); p[1] = __builtin_arm_get_fpscr(); } in the above example the second read is currently CSE'd into the first read, this is because llvm isn't aware that the write done by __builtin_arm_set_fpscr effects the same register that __builtin_arm_get_fpscr reads from, to fix this problem I've removed the property IntrNoMem so that __builtin_arm_get_fpscr is treated as a memory access. Differential Revision: https://reviews.llvm.org/D30542 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296865 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IR/IntrinsicsARM.td | 2 +- test/CodeGen/ARM/fpscr-intrinsics.ll | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/ARM/fpscr-intrinsics.ll diff --git a/include/llvm/IR/IntrinsicsARM.td b/include/llvm/IR/IntrinsicsARM.td index 24239689a62..18ed24be56d 100644 --- a/include/llvm/IR/IntrinsicsARM.td +++ b/include/llvm/IR/IntrinsicsARM.td @@ -67,7 +67,7 @@ def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">, // VFP def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">, - Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + Intrinsic<[llvm_i32_ty], [], []>; def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">, Intrinsic<[], [llvm_i32_ty], []>; def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty], diff --git a/test/CodeGen/ARM/fpscr-intrinsics.ll b/test/CodeGen/ARM/fpscr-intrinsics.ll new file mode 100644 index 00000000000..db24d0d6420 --- /dev/null +++ b/test/CodeGen/ARM/fpscr-intrinsics.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -O0 -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -O3 -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s + +; Function Attrs: nounwind +define void @fn1(i32* nocapture %p) local_unnamed_addr { +entry: + ; CHECK: vmrs r{{[0-9]+}}, fpscr + %0 = tail call i32 @llvm.arm.get.fpscr() + store i32 %0, i32* %p, align 4 + ; CHECK: vmsr fpscr, r{{[0-9]+}} + tail call void @llvm.arm.set.fpscr(i32 1) + ; CHECK: vmrs r{{[0-9]+}}, fpscr + %1 = tail call i32 @llvm.arm.get.fpscr() + %arrayidx1 = getelementptr inbounds i32, i32* %p, i32 1 + store i32 %1, i32* %arrayidx1, align 4 + ret void +} + +; Function Attrs: nounwind readonly +declare i32 @llvm.arm.get.fpscr() + +; Function Attrs: nounwind writeonly +declare void @llvm.arm.set.fpscr(i32) -- 2.11.0