From 83ff5e44f4bd0388e16160f0ee38cb686c4963af Mon Sep 17 00:00:00 2001
From: Chad Rosier <mcrosier@codeaurora.org>
Date: Tue, 21 Nov 2017 18:08:34 +0000
Subject: [PATCH] [AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having*
 side effects.

This partially reverts r298851.  The the underlying issue is that we don't
currently model the dependency between mrs (read system register) and
msr (write system register) instructions.

Something like the below should never be reordered:

 msr TPIDR_EL0, x0  ;; set thread pointer
 mrs x8, TPIDR_EL0  ;; read thread pointer

but was being reordered after r298851.  The functional part of the patch
that wasn't reverted needed to remain in place in order to not break
r299462.

PR35317

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318788 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/AArch64/AArch64InstrInfo.td |  3 +-
 test/CodeGen/AArch64/thread-pointer.ll | 60 ----------------------------------
 2 files changed, 1 insertion(+), 62 deletions(-)
 delete mode 100644 test/CodeGen/AArch64/thread-pointer.ll

diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td
index a3616351c63..841265c3367 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/lib/Target/AArch64/AArch64InstrInfo.td
@@ -552,8 +552,7 @@ def MSRpstateImm1 : MSRpstateImm0_1;
 def MSRpstateImm4 : MSRpstateImm0_15;
 
 // The thread pointer (on Linux, at least, where this has been implemented) is
-// TPIDR_EL0.  Add pseudo op so we can mark it as not having any side effects.
-let hasSideEffects = 0 in
+// TPIDR_EL0.
 def MOVbaseTLS : Pseudo<(outs GPR64:$dst), (ins),
                        [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[WriteSys]>;
 
diff --git a/test/CodeGen/AArch64/thread-pointer.ll b/test/CodeGen/AArch64/thread-pointer.ll
deleted file mode 100644
index 7fea719436f..00000000000
--- a/test/CodeGen/AArch64/thread-pointer.ll
+++ /dev/null
@@ -1,60 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s
-
-@x = thread_local local_unnamed_addr global i32 0, align 4
-@y = thread_local local_unnamed_addr global i32 0, align 4
-
-; Machine LICM should hoist the mrs into the loop preheader.
-; CHECK-LABEL: @test1
-; CHECK: BB#1:
-; CHECK:   mrs x[[BASE:[0-9]+]], TPIDR_EL0
-; CHECK:   add x[[REG1:[0-9]+]], x[[BASE]], :tprel_hi12:x
-; CHECK:   add x[[REG2:[0-9]+]], x[[REG1]], :tprel_lo12_nc:x
-;
-; CHECK: .LBB0_2:
-; CHECK:   ldr w0, [x[[REG2]]]
-; CHECK:   bl bar
-; CHECK:   subs w[[REG3:[0-9]+]], w{{[0-9]+}}, #1
-; CHECK:   b.ne .LBB0_2
-
-define void @test1(i32 %n) local_unnamed_addr {
-entry:
-  %cmp3 = icmp sgt i32 %n, 0
-  br i1 %cmp3, label %bb1, label %bb2
-
-bb1:
-  br label %for.body
-
-for.body:
-  %i.04 = phi i32 [ %inc, %for.body ], [ 0, %bb1 ]
-  %0 = load i32, i32* @x, align 4
-  tail call void @bar(i32 %0) #2
-  %inc = add nuw nsw i32 %i.04, 1
-  %exitcond = icmp eq i32 %inc, %n
-  br i1 %exitcond, label %bb2, label %for.body
-
-bb2:
-  ret void
-}
-
-; Machine CSE should combine the the mrs between the load of %x and %y.
-; CHECK-LABEL: @test2
-; CHECK: mrs x{{[0-9]+}}, TPIDR_EL0
-; CHECK-NOT: mrs x{{[0-9]+}}, TPIDR_EL0
-; CHECK: ret
-define void @test2(i32 %c) local_unnamed_addr #0 {
-entry:
-  %0 = load i32, i32* @x, align 4
-  tail call void @bar(i32 %0) #2
-  %cmp = icmp eq i32 %c, 0
-  br i1 %cmp, label %if.end, label %if.then
-
-if.then:
-  %1 = load i32, i32* @y, align 4
-  tail call void @bar(i32 %1) #2
-  br label %if.end
-
-if.end:
-  ret void
-}
-
-declare void @bar(i32) local_unnamed_addr
-- 
2.11.0