From 83ffc6f26186a464d8df0a79f6bb0261cc6f220c Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sun, 23 Apr 2017 19:56:49 +0000
Subject: [PATCH] [X86][SSE] Add missing scheduling latency/throughput test for
 PINSRW

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301136 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/X86/sse2-schedule.ll | 46 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/test/CodeGen/X86/sse2-schedule.ll b/test/CodeGen/X86/sse2-schedule.ll
index 33a4f413b68..9469b8f07b0 100644
--- a/test/CodeGen/X86/sse2-schedule.ll
+++ b/test/CodeGen/X86/sse2-schedule.ll
@@ -3545,6 +3545,52 @@ define i16 @test_pextrw(<8 x i16> %a0) {
   ret i16 %1
 }
 
+define <8 x i16> @test_pinsrw(<8 x i16> %a0, i16 %a1, i16 *%a2) {
+; GENERIC-LABEL: test_pinsrw:
+; GENERIC:       # BB#0:
+; GENERIC-NEXT:    pinsrw $1, %edi, %xmm0
+; GENERIC-NEXT:    pinsrw $3, (%rsi), %xmm0
+; GENERIC-NEXT:    retq
+;
+; ATOM-LABEL: test_pinsrw:
+; ATOM:       # BB#0:
+; ATOM-NEXT:    pinsrw $1, %edi, %xmm0
+; ATOM-NEXT:    pinsrw $3, (%rsi), %xmm0
+; ATOM-NEXT:    nop
+; ATOM-NEXT:    nop
+; ATOM-NEXT:    nop
+; ATOM-NEXT:    nop
+; ATOM-NEXT:    retq
+;
+; SLM-LABEL: test_pinsrw:
+; SLM:       # BB#0:
+; SLM-NEXT:    pinsrw $1, %edi, %xmm0 # sched: [1:1.00]
+; SLM-NEXT:    pinsrw $3, (%rsi), %xmm0 # sched: [4:1.00]
+; SLM-NEXT:    retq # sched: [4:1.00]
+;
+; SANDY-LABEL: test_pinsrw:
+; SANDY:       # BB#0:
+; SANDY-NEXT:    vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [1:0.50]
+; SANDY-NEXT:    vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [5:0.50]
+; SANDY-NEXT:    retq # sched: [5:1.00]
+;
+; HASWELL-LABEL: test_pinsrw:
+; HASWELL:       # BB#0:
+; HASWELL-NEXT:    vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [1:1.00]
+; HASWELL-NEXT:    vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [5:1.00]
+; HASWELL-NEXT:    retq # sched: [1:1.00]
+;
+; BTVER2-LABEL: test_pinsrw:
+; BTVER2:       # BB#0:
+; BTVER2-NEXT:    vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [1:0.50]
+; BTVER2-NEXT:    vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT:    retq # sched: [4:1.00]
+  %1 = insertelement <8 x i16> %a0, i16 %a1, i32 1
+  %2 = load i16, i16 *%a2
+  %3 = insertelement <8 x i16> %1, i16 %2, i32 3
+  ret <8 x i16> %3
+}
+
 define <4 x i32> @test_pmaddwd(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
 ; GENERIC-LABEL: test_pmaddwd:
 ; GENERIC:       # BB#0:
-- 
2.11.0