From 842b206f268a69d7def87b990f272a514c49837b Mon Sep 17 00:00:00 2001 From: Taylor Simpson Date: Thu, 27 Apr 2023 16:00:10 -0700 Subject: [PATCH] Hexagon (target/hexagon) Move pred_written to DisasContext The pred_written variable in the CPUHexagonState is only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-20-tsimpson@quicinc.com> --- target/hexagon/cpu.h | 2 -- target/hexagon/genptr.c | 2 +- target/hexagon/helper.h | 2 +- target/hexagon/op_helper.c | 5 +++-- target/hexagon/translate.c | 9 ++++----- target/hexagon/translate.h | 2 +- 6 files changed, 10 insertions(+), 12 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 2b4f77fb8e..7673f9f32d 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -98,8 +98,6 @@ typedef struct CPUArchState { target_ulong this_PC; target_ulong reg_written[TOTAL_PER_THREAD_REGS]; - target_ulong pred_written; - MemLog mem_log_stores[STORES_MAX]; target_ulong pkt_has_store_s1; target_ulong dczero_addr; diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 1f69f4f922..785778759e 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -151,7 +151,7 @@ void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) tcg_gen_and_tl(pred, pred, base_val); } if (HEX_DEBUG) { - tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum); + tcg_gen_ori_tl(ctx->pred_written, ctx->pred_written, 1 << pnum); } set_bit(pnum, ctx->pregs_written); } diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 4b750d0351..f3b298beee 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -21,7 +21,7 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32) DEF_HELPER_1(debug_start_packet, void, env) DEF_HELPER_FLAGS_3(debug_check_store_width, TCG_CALL_NO_WG, void, env, int, int) -DEF_HELPER_FLAGS_3(debug_commit_end, TCG_CALL_NO_WG, void, env, int, int) +DEF_HELPER_FLAGS_4(debug_commit_end, TCG_CALL_NO_WG, void, env, int, int, int) DEF_HELPER_2(commit_store, void, env, int) DEF_HELPER_3(gather_store, void, env, i32, int) DEF_HELPER_1(commit_hvx_stores, void, env) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 26fba9f5d6..f9021efc7e 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -203,7 +203,8 @@ static void print_store(CPUHexagonState *env, int slot) } /* This function is a handy place to set a breakpoint */ -void HELPER(debug_commit_end)(CPUHexagonState *env, int has_st0, int has_st1) +void HELPER(debug_commit_end)(CPUHexagonState *env, + int pred_written, int has_st0, int has_st1) { bool reg_printed = false; bool pred_printed = false; @@ -225,7 +226,7 @@ void HELPER(debug_commit_end)(CPUHexagonState *env, int has_st0, int has_st1) } for (i = 0; i < NUM_PREGS; i++) { - if (env->pred_written & (1 << i)) { + if (pred_written & (1 << i)) { if (!pred_printed) { HEX_DEBUG_LOG("Predicates written\n"); pred_printed = true; diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 459aace921..a585cc8cfd 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -46,7 +46,6 @@ TCGv hex_slot_cancelled; TCGv hex_branch_taken; TCGv hex_new_value_usr; TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; -TCGv hex_pred_written; TCGv hex_store_addr[STORES_MAX]; TCGv hex_store_width[STORES_MAX]; TCGv hex_store_val32[STORES_MAX]; @@ -549,7 +548,8 @@ static void gen_start_packet(DisasContext *ctx) } } if (HEX_DEBUG) { - tcg_gen_movi_tl(hex_pred_written, 0); + ctx->pred_written = tcg_temp_new(); + tcg_gen_movi_tl(ctx->pred_written, 0); } /* Preload the predicated registers into get_result_gpr(ctx, i) */ @@ -1007,7 +1007,8 @@ static void gen_commit_packet(DisasContext *ctx) tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); /* Handy place to set a breakpoint at the end of execution */ - gen_helper_debug_commit_end(cpu_env, has_st0, has_st1); + gen_helper_debug_commit_end(cpu_env, ctx->pred_written, + has_st0, has_st1); } if (pkt->vhist_insn != NULL) { @@ -1200,8 +1201,6 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, pred[i]), hexagon_prednames[i]); } - hex_pred_written = tcg_global_mem_new(cpu_env, - offsetof(CPUHexagonState, pred_written), "pred_written"); hex_this_PC = tcg_global_mem_new(cpu_env, offsetof(CPUHexagonState, this_PC), "this_PC"); hex_slot_cancelled = tcg_global_mem_new(cpu_env, diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index fdfa1b6fe3..a9f1ccee24 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -71,6 +71,7 @@ typedef struct DisasContext { bool has_hvx_helper; TCGv new_value[TOTAL_PER_THREAD_REGS]; TCGv new_pred_value[NUM_PREGS]; + TCGv pred_written; } DisasContext; static inline void ctx_log_pred_write(DisasContext *ctx, int pnum) @@ -194,7 +195,6 @@ extern TCGv hex_slot_cancelled; extern TCGv hex_branch_taken; extern TCGv hex_new_value_usr; extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; -extern TCGv hex_pred_written; extern TCGv hex_store_addr[STORES_MAX]; extern TCGv hex_store_width[STORES_MAX]; extern TCGv hex_store_val32[STORES_MAX]; -- 2.11.0