From 84c6a591f31ec75aadf82dbee88d3593790054ab Mon Sep 17 00:00:00 2001 From: David Greene Date: Wed, 10 Jul 2019 18:25:58 +0000 Subject: [PATCH] Revert "[System Model] [TTI] Update cache and prefetch TTI interfaces" This broke some PPC prefetching tests. This reverts commit 9fdfb045ae8bb643ab0d0455dcf9ecaea3b1eb3c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365680 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Analysis/TargetTransformInfo.h | 70 +++++++---------------- include/llvm/Analysis/TargetTransformInfoImpl.h | 12 ++-- include/llvm/CodeGen/BasicTTIImpl.h | 28 --------- include/llvm/MC/MCSubtargetInfo.h | 44 -------------- lib/MC/MCSubtargetInfo.cpp | 25 -------- lib/Target/AArch64/AArch64Subtarget.h | 8 +-- lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 16 ++++++ lib/Target/AArch64/AArch64TargetTransformInfo.h | 8 +++ lib/Target/Hexagon/HexagonTargetTransformInfo.h | 4 +- lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 4 +- lib/Target/PowerPC/PPCTargetTransformInfo.h | 4 +- lib/Target/SystemZ/SystemZTargetTransformInfo.h | 6 +- 12 files changed, 63 insertions(+), 166 deletions(-) diff --git a/include/llvm/Analysis/TargetTransformInfo.h b/include/llvm/Analysis/TargetTransformInfo.h index ec6815bd11e..af1a12dc18d 100644 --- a/include/llvm/Analysis/TargetTransformInfo.h +++ b/include/llvm/Analysis/TargetTransformInfo.h @@ -812,20 +812,18 @@ public: /// \return The associativity of the cache level, if available. llvm::Optional getCacheAssociativity(CacheLevel Level) const; - /// \return How much before a load we should place the prefetch - /// instruction. This is currently measured in number of - /// instructions. + /// \return How much before a load we should place the prefetch instruction. + /// This is currently measured in number of instructions. unsigned getPrefetchDistance() const; - /// \return Some HW prefetchers can handle accesses up to a certain - /// constant stride. This is the minimum stride in bytes where it - /// makes sense to start adding SW prefetches. The default is 1, - /// i.e. prefetch with any stride. + /// \return Some HW prefetchers can handle accesses up to a certain constant + /// stride. This is the minimum stride in bytes where it makes sense to start + /// adding SW prefetches. The default is 1, i.e. prefetch with any stride. unsigned getMinPrefetchStride() const; - /// \return The maximum number of iterations to prefetch ahead. If - /// the required number of iterations is more than this number, no - /// prefetching is performed. + /// \return The maximum number of iterations to prefetch ahead. If the + /// required number of iterations is more than this number, no prefetching is + /// performed. unsigned getMaxPrefetchIterationsAhead() const; /// \return The maximum interleave factor that any transform should try to @@ -1224,26 +1222,12 @@ public: virtual unsigned getMinimumVF(unsigned ElemWidth) const = 0; virtual bool shouldConsiderAddressTypePromotion( const Instruction &I, bool &AllowPromotionWithoutCommonHeader) = 0; - virtual unsigned getCacheLineSize() const = 0; - virtual llvm::Optional getCacheSize(CacheLevel Level) const = 0; - virtual llvm::Optional getCacheAssociativity(CacheLevel Level) const = 0; - - /// \return How much before a load we should place the prefetch - /// instruction. This is currently measured in number of - /// instructions. - virtual unsigned getPrefetchDistance() const = 0; - - /// \return Some HW prefetchers can handle accesses up to a certain - /// constant stride. This is the minimum stride in bytes where it - /// makes sense to start adding SW prefetches. The default is 1, - /// i.e. prefetch with any stride. - virtual unsigned getMinPrefetchStride() const = 0; - - /// \return The maximum number of iterations to prefetch ahead. If - /// the required number of iterations is more than this number, no - /// prefetching is performed. - virtual unsigned getMaxPrefetchIterationsAhead() const = 0; - + virtual unsigned getCacheLineSize() = 0; + virtual llvm::Optional getCacheSize(CacheLevel Level) = 0; + virtual llvm::Optional getCacheAssociativity(CacheLevel Level) = 0; + virtual unsigned getPrefetchDistance() = 0; + virtual unsigned getMinPrefetchStride() = 0; + virtual unsigned getMaxPrefetchIterationsAhead() = 0; virtual unsigned getMaxInterleaveFactor(unsigned VF) = 0; virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind Opd1Info, @@ -1583,36 +1567,22 @@ public: return Impl.shouldConsiderAddressTypePromotion( I, AllowPromotionWithoutCommonHeader); } - unsigned getCacheLineSize() const override { + unsigned getCacheLineSize() override { return Impl.getCacheLineSize(); } - llvm::Optional getCacheSize(CacheLevel Level) const override { + llvm::Optional getCacheSize(CacheLevel Level) override { return Impl.getCacheSize(Level); } - llvm::Optional getCacheAssociativity(CacheLevel Level) const override { + llvm::Optional getCacheAssociativity(CacheLevel Level) override { return Impl.getCacheAssociativity(Level); } - - /// Return the preferred prefetch distance in terms of instructions. - /// - unsigned getPrefetchDistance() const override { - return Impl.getPrefetchDistance(); - } - - /// Return the minimum stride necessary to trigger software - /// prefetching. - /// - unsigned getMinPrefetchStride() const override { + unsigned getPrefetchDistance() override { return Impl.getPrefetchDistance(); } + unsigned getMinPrefetchStride() override { return Impl.getMinPrefetchStride(); } - - /// Return the maximum prefetch distance in terms of loop - /// iterations. - /// - unsigned getMaxPrefetchIterationsAhead() const override { + unsigned getMaxPrefetchIterationsAhead() override { return Impl.getMaxPrefetchIterationsAhead(); } - unsigned getMaxInterleaveFactor(unsigned VF) override { return Impl.getMaxInterleaveFactor(VF); } diff --git a/include/llvm/Analysis/TargetTransformInfoImpl.h b/include/llvm/Analysis/TargetTransformInfoImpl.h index 0f031218544..a9383e795fc 100644 --- a/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -363,9 +363,9 @@ public: return false; } - unsigned getCacheLineSize() const { return 0; } + unsigned getCacheLineSize() { return 0; } - llvm::Optional getCacheSize(TargetTransformInfo::CacheLevel Level) const { + llvm::Optional getCacheSize(TargetTransformInfo::CacheLevel Level) { switch (Level) { case TargetTransformInfo::CacheLevel::L1D: LLVM_FALLTHROUGH; @@ -377,7 +377,7 @@ public: } llvm::Optional getCacheAssociativity( - TargetTransformInfo::CacheLevel Level) const { + TargetTransformInfo::CacheLevel Level) { switch (Level) { case TargetTransformInfo::CacheLevel::L1D: LLVM_FALLTHROUGH; @@ -388,11 +388,11 @@ public: llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); } - unsigned getPrefetchDistance() const { return 0; } + unsigned getPrefetchDistance() { return 0; } - unsigned getMinPrefetchStride() const { return 1; } + unsigned getMinPrefetchStride() { return 1; } - unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; } + unsigned getMaxPrefetchIterationsAhead() { return UINT_MAX; } unsigned getMaxInterleaveFactor(unsigned VF) { return 1; } diff --git a/include/llvm/CodeGen/BasicTTIImpl.h b/include/llvm/CodeGen/BasicTTIImpl.h index 473ef7c365e..173be72e7fe 100644 --- a/include/llvm/CodeGen/BasicTTIImpl.h +++ b/include/llvm/CodeGen/BasicTTIImpl.h @@ -506,34 +506,6 @@ public: return BaseT::getInstructionLatency(I); } - virtual Optional - getCacheSize(TargetTransformInfo::CacheLevel Level) const { - return Optional( - getST()->getCacheSize(static_cast(Level))); - } - - virtual Optional - getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const { - return Optional( - getST()->getCacheAssociativity(static_cast(Level))); - } - - virtual unsigned getCacheLineSize() const { - return getST()->getCacheLineSize(); - } - - virtual unsigned getPrefetchDistance() const { - return getST()->getPrefetchDistance(); - } - - virtual unsigned getMinPrefetchStride() const { - return getST()->getMinPrefetchStride(); - } - - virtual unsigned getMaxPrefetchIterationsAhead() const { - return getST()->getMaxPrefetchIterationsAhead(); - } - /// @} /// \name Vector TTI Implementations diff --git a/include/llvm/MC/MCSubtargetInfo.h b/include/llvm/MC/MCSubtargetInfo.h index a275ec7bb51..9490a6eceda 100644 --- a/include/llvm/MC/MCSubtargetInfo.h +++ b/include/llvm/MC/MCSubtargetInfo.h @@ -221,50 +221,6 @@ public: auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU); return Found != ProcDesc.end() && StringRef(Found->Key) == CPU; } - - /// Return the cache size in bytes for the given level of cache. - /// Level is zero-based, so a value of zero means the first level of - /// cache. - /// - virtual Optional getCacheSize(unsigned Level) const; - - /// Return the cache associatvity for the given level of cache. - /// Level is zero-based, so a value of zero means the first level of - /// cache. - /// - virtual Optional getCacheAssociativity(unsigned Level) const; - - /// Return the target cache line size in bytes at a given level. - /// - virtual Optional getCacheLineSize(unsigned Level) const; - - /// Return the target cache line size in bytes. By default, return - /// the line size for the bottom-most level of cache. This provides - /// a more convenient interface for the common case where all cache - /// levels have the same line size. Return zero if there is no - /// cache model. - /// - virtual unsigned getCacheLineSize() const { - Optional Size = getCacheLineSize(0); - if (Size) - return *Size; - - return 0; - } - - /// Return the preferred prefetch distance in terms of instructions. - /// - virtual unsigned getPrefetchDistance() const; - - /// Return the maximum prefetch distance in terms of loop - /// iterations. - /// - virtual unsigned getMaxPrefetchIterationsAhead() const; - - /// Return the minimum stride necessary to trigger software - /// prefetching. - /// - virtual unsigned getMinPrefetchStride() const; }; } // end namespace llvm diff --git a/lib/MC/MCSubtargetInfo.cpp b/lib/MC/MCSubtargetInfo.cpp index 00801deef8f..5fd48d9e101 100644 --- a/lib/MC/MCSubtargetInfo.cpp +++ b/lib/MC/MCSubtargetInfo.cpp @@ -315,28 +315,3 @@ void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const { InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles, ForwardingPaths); } - -Optional MCSubtargetInfo::getCacheSize(unsigned Level) const { - return Optional(); -} - -Optional -MCSubtargetInfo::getCacheAssociativity(unsigned Level) const { - return Optional(); -} - -Optional MCSubtargetInfo::getCacheLineSize(unsigned Level) const { - return Optional(); -} - -unsigned MCSubtargetInfo::getPrefetchDistance() const { - return 0; -} - -unsigned MCSubtargetInfo::getMaxPrefetchIterationsAhead() const { - return 0; -} - -unsigned MCSubtargetInfo::getMinPrefetchStride() const { - return 0; -} diff --git a/lib/Target/AArch64/AArch64Subtarget.h b/lib/Target/AArch64/AArch64Subtarget.h index 31ce4f95634..0c84cfb8329 100644 --- a/lib/Target/AArch64/AArch64Subtarget.h +++ b/lib/Target/AArch64/AArch64Subtarget.h @@ -344,10 +344,10 @@ public: unsigned getVectorInsertExtractBaseCost() const { return VectorInsertExtractBaseCost; } - unsigned getCacheLineSize() const override { return CacheLineSize; } - unsigned getPrefetchDistance() const override { return PrefetchDistance; } - unsigned getMinPrefetchStride() const override { return MinPrefetchStride; } - unsigned getMaxPrefetchIterationsAhead() const override { + unsigned getCacheLineSize() const { return CacheLineSize; } + unsigned getPrefetchDistance() const { return PrefetchDistance; } + unsigned getMinPrefetchStride() const { return MinPrefetchStride; } + unsigned getMaxPrefetchIterationsAhead() const { return MaxPrefetchIterationsAhead; } unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; } diff --git a/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index 99a2cc40af6..a4b78f2a7d6 100644 --- a/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -879,6 +879,22 @@ bool AArch64TTIImpl::shouldConsiderAddressTypePromotion( return Considerable; } +unsigned AArch64TTIImpl::getCacheLineSize() { + return ST->getCacheLineSize(); +} + +unsigned AArch64TTIImpl::getPrefetchDistance() { + return ST->getPrefetchDistance(); +} + +unsigned AArch64TTIImpl::getMinPrefetchStride() { + return ST->getMinPrefetchStride(); +} + +unsigned AArch64TTIImpl::getMaxPrefetchIterationsAhead() { + return ST->getMaxPrefetchIterationsAhead(); +} + bool AArch64TTIImpl::useReductionIntrinsic(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const { assert(isa(Ty) && "Expected Ty to be a vector type"); diff --git a/lib/Target/AArch64/AArch64TargetTransformInfo.h b/lib/Target/AArch64/AArch64TargetTransformInfo.h index 415bff3677c..10c15a139b4 100644 --- a/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -153,6 +153,14 @@ public: shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader); + unsigned getCacheLineSize(); + + unsigned getPrefetchDistance(); + + unsigned getMinPrefetchStride(); + + unsigned getMaxPrefetchIterationsAhead(); + bool shouldExpandReduction(const IntrinsicInst *II) const { return false; } diff --git a/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/lib/Target/Hexagon/HexagonTargetTransformInfo.h index 12ede503af8..27e8fc01900 100644 --- a/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -68,8 +68,8 @@ public: bool shouldFavorPostInc() const; // L1 cache prefetch. - unsigned getPrefetchDistance() const override; - unsigned getCacheLineSize() const override; + unsigned getPrefetchDistance() const; + unsigned getCacheLineSize() const; /// @} diff --git a/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 8f4d3fd4e5a..ff3dfbfaca0 100644 --- a/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -613,7 +613,7 @@ unsigned PPCTTIImpl::getRegisterBitWidth(bool Vector) const { } -unsigned PPCTTIImpl::getCacheLineSize() const { +unsigned PPCTTIImpl::getCacheLineSize() { // Check first if the user specified a custom line size. if (CacheLineSize.getNumOccurrences() > 0) return CacheLineSize; @@ -628,7 +628,7 @@ unsigned PPCTTIImpl::getCacheLineSize() const { return 64; } -unsigned PPCTTIImpl::getPrefetchDistance() const { +unsigned PPCTTIImpl::getPrefetchDistance() { // This seems like a reasonable default for the BG/Q (this pass is enabled, by // default, only on the BG/Q). return 300; diff --git a/lib/Target/PowerPC/PPCTargetTransformInfo.h b/lib/Target/PowerPC/PPCTargetTransformInfo.h index e66ba979af1..5d76ee418b6 100644 --- a/lib/Target/PowerPC/PPCTargetTransformInfo.h +++ b/lib/Target/PowerPC/PPCTargetTransformInfo.h @@ -74,8 +74,8 @@ public: bool enableInterleavedAccessVectorization(); unsigned getNumberOfRegisters(bool Vector); unsigned getRegisterBitWidth(bool Vector) const; - unsigned getCacheLineSize() const override; - unsigned getPrefetchDistance() const override; + unsigned getCacheLineSize(); + unsigned getPrefetchDistance(); unsigned getMaxInterleaveFactor(unsigned VF); int vectorCostAdjustment(int Cost, unsigned Opcode, Type *Ty1, Type *Ty2); int getArithmeticInstrCost( diff --git a/lib/Target/SystemZ/SystemZTargetTransformInfo.h b/lib/Target/SystemZ/SystemZTargetTransformInfo.h index bd9d2cd99c2..16ce2ef1d7a 100644 --- a/lib/Target/SystemZ/SystemZTargetTransformInfo.h +++ b/lib/Target/SystemZ/SystemZTargetTransformInfo.h @@ -59,9 +59,9 @@ public: unsigned getNumberOfRegisters(bool Vector); unsigned getRegisterBitWidth(bool Vector) const; - unsigned getCacheLineSize() const override { return 256; } - unsigned getPrefetchDistance() const override { return 2000; } - unsigned getMinPrefetchStride() const override { return 2048; } + unsigned getCacheLineSize() { return 256; } + unsigned getPrefetchDistance() { return 2000; } + unsigned getMinPrefetchStride() { return 2048; } bool hasDivRemOp(Type *DataType, bool IsSigned); bool prefersVectorizedAddressing() { return false; } -- 2.11.0