From 8541eae72cf1ee58459aa5829cd9e00df9ef5251 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Mon, 28 Mar 2016 17:52:08 +0000 Subject: [PATCH] [PowerPC] On the A2, popcnt[dw] are very slow The A2 cores support the popcntw/popcntd instructions, but they're microcoded, and slower than our default software emulation. Specifically, popcnt[dw] take approximately 74 cycles, whereas our software emulation takes only 24-28 cycles. I've added a new target feature to indicate a slow popcnt[dw], instead of just removing the existing target feature from the a2/a2q processor models, because: 1. This allows us to return more accurate information via the TTI interface (I recognize that this currently makes no practical difference) 2. Is hopefully easier to understand (it allows the core's features to match its manual while still having the desired effect). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264600 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPC.td | 15 +++++++++++---- lib/Target/PowerPC/PPCISelLowering.cpp | 2 +- lib/Target/PowerPC/PPCSubtarget.cpp | 1 + lib/Target/PowerPC/PPCSubtarget.h | 2 ++ lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 2 +- test/CodeGen/PowerPC/popcnt.ll | 22 ++++++++++++++++++---- 6 files changed, 34 insertions(+), 10 deletions(-) diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index 9e22701d01c..fc516d913f4 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -155,6 +155,12 @@ def FeatureFloat128 : def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", "Treat vector data stream cache control instructions as deprecated">; +// Note that for the a2/a2q processor models we should not use popcnt[dw] by +// default. These processors do support the instructions, but they're +// microcoded, and the software emulation is about twice as fast. +def SlowPOPCNTD : SubtargetFeature<"slow-popcntd","SlowPOPCNTD", "true", + "The popcnt[dw] instructions are slow">; + /* Since new processors generally contain a superset of features of those that came before them, the idea is to make implementations of new processors less error prone and easier to read. @@ -337,16 +343,17 @@ def : ProcessorModel<"a2", PPCA2Model, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureFPRND, FeatureFPCVT, FeatureISEL, - FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit - /*, Feature64BitRegs */, FeatureMFTB]>; + FeaturePOPCNTD, SlowPOPCNTD, FeatureCMPB, FeatureLDBRX, + Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; def : ProcessorModel<"a2q", PPCA2Model, [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureFPRND, FeatureFPCVT, FeatureISEL, - FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit - /*, Feature64BitRegs */, FeatureQPX, FeatureMFTB]>; + FeaturePOPCNTD, SlowPOPCNTD, FeatureCMPB, FeatureLDBRX, + Feature64Bit /*, Feature64BitRegs */, FeatureQPX, + FeatureMFTB]>; def : ProcessorModel<"pwr3", G5Model, [DirectivePwr3, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index ac3523537a5..6a16e015a73 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -214,7 +214,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); - if (Subtarget.hasPOPCNTD()) { + if (Subtarget.hasPOPCNTD() && !Subtarget.isPOPCNTDSlow()) { setOperationAction(ISD::CTPOP, MVT::i32 , Legal); setOperationAction(ISD::CTPOP, MVT::i64 , Legal); } else { diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp index 359c2eb85b3..6ab79c1b57c 100644 --- a/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/lib/Target/PowerPC/PPCSubtarget.cpp @@ -105,6 +105,7 @@ void PPCSubtarget::initializeEnvironment() { HasHTM = false; HasFusion = false; HasFloat128 = false; + SlowPOPCNTD = false; } void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { diff --git a/lib/Target/PowerPC/PPCSubtarget.h b/lib/Target/PowerPC/PPCSubtarget.h index 7ff77ce2522..fc4ba3f7cc3 100644 --- a/lib/Target/PowerPC/PPCSubtarget.h +++ b/lib/Target/PowerPC/PPCSubtarget.h @@ -124,6 +124,7 @@ protected: bool HasHTM; bool HasFusion; bool HasFloat128; + bool SlowPOPCNTD; /// When targeting QPX running a stock PPC64 Linux kernel where the stack /// alignment has not been changed, we need to keep the 16-byte alignment @@ -248,6 +249,7 @@ public: bool isE500() const { return IsE500; } bool isFeatureMFTB() const { return FeatureMFTB; } bool isDeprecatedDST() const { return DeprecatedDST; } + bool isPOPCNTDSlow() const { return SlowPOPCNTD; } bool hasICBT() const { return HasICBT; } bool hasInvariantFunctionDescriptors() const { return HasInvariantFunctionDescriptors; diff --git a/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 9212e916f59..390faf59961 100644 --- a/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -43,7 +43,7 @@ TargetTransformInfo::PopcntSupportKind PPCTTIImpl::getPopcntSupport(unsigned TyWidth) { assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); if (ST->hasPOPCNTD() && TyWidth <= 64) - return TTI::PSK_FastHardware; + return ST->isPOPCNTDSlow() ? TTI::PSK_SlowHardware : TTI::PSK_FastHardware; return TTI::PSK_Software; } diff --git a/test/CodeGen/PowerPC/popcnt.ll b/test/CodeGen/PowerPC/popcnt.ll index b304d72aede..79fc40e58a5 100644 --- a/test/CodeGen/PowerPC/popcnt.ll +++ b/test/CodeGen/PowerPC/popcnt.ll @@ -1,37 +1,51 @@ ; RUN: llc -march=ppc64 -mattr=+popcntd < %s | FileCheck %s +; RUN: llc -march=ppc64 -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -march=ppc64 -mcpu=a2q < %s | FileCheck %s --check-prefix=SLOWPC define i8 @cnt8(i8 %x) nounwind readnone { %cnt = tail call i8 @llvm.ctpop.i8(i8 %x) ret i8 %cnt -; CHECK: @cnt8 +; CHECK-LABEL: @cnt8 ; CHECK: rlwinm ; CHECK: popcntw ; CHECK: blr + +; SLOWPC-LABEL: @cnt8 +; SLOWPC-NOT: popcnt } define i16 @cnt16(i16 %x) nounwind readnone { %cnt = tail call i16 @llvm.ctpop.i16(i16 %x) ret i16 %cnt -; CHECK: @cnt16 +; CHECK-LABEL: @cnt16 ; CHECK: rlwinm ; CHECK: popcntw ; CHECK: blr + +; SLOWPC-LABEL: @cnt16 +; SLOWPC-NOT: popcnt } define i32 @cnt32(i32 %x) nounwind readnone { %cnt = tail call i32 @llvm.ctpop.i32(i32 %x) ret i32 %cnt -; CHECK: @cnt32 +; CHECK-LABEL: @cnt32 ; CHECK: popcntw ; CHECK: blr + +; SLOWPC-LABEL: @cnt32 +; SLOWPC-NOT: popcnt } define i64 @cnt64(i64 %x) nounwind readnone { %cnt = tail call i64 @llvm.ctpop.i64(i64 %x) ret i64 %cnt -; CHECK: @cnt64 +; CHECK-LABEL: @cnt64 ; CHECK: popcntd ; CHECK: blr + +; SLOWPC-LABEL: @cnt64 +; SLOWPC-NOT: popcnt } declare i8 @llvm.ctpop.i8(i8) nounwind readnone -- 2.11.0