From 86374326acd77edf6d1d180e46ca7779c636fa1a Mon Sep 17 00:00:00 2001 From: nathan Date: Tue, 8 Nov 2005 11:15:11 +0000 Subject: [PATCH] bfd: Add ms2. * archures.c (bfd_mach_ms2): Define. * cpu-ms1.c (arch_info_struct): Add ms2 stanza. * elf32-ms1.c (elf32_ms1_machine): Add ms2 case. (ms1_elf_merge_private_bfd_data): Remove unused variables. Add correct merging logic, with workaround. (ms1_elf_print_private_bfd_data): Add ms2 case. * reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc. * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. cpu: Add ms2 * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and model. (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr, f-cb2incr, f-rc3): New fields. (LOOP): New instruction. (JAL-HAZARD): New hazard. (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr): New operands. (mul, muli, dbnz, iflush): Enable for ms2 (jal, reti): Has JAL-HAZARD. (ldctxt, ldfb, stfb): Only ms1. (fbcb): Only ms1,ms1-003. (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs, fbcbincrs, mfbcbincrs): Enable for ms2. (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns. * ms1.opc (parse_loopsize): New. (parse_imm16): hi16/lo16 relocs are applicable to IMM16L. (print_pcrel): New. gas: Add ms2. * config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1. (ms1_architectures): Add ms2. (md_parse_option): Add ms2. (md_show_usage): Add ms2. (md_assemble): Add JAL_HAZARD detection logic. (md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case. * doc/c-ms1.texi: New. * doc/all.texi: Add MS1. * doc/Makefile.am (CPU_DOCS): Add c-ms1.texi. * doc/Makefile.in: Rebuilt. * doc/Makefile: Rebuilt. gas/testsuite: Add ms2. * gas/ms1/allinsn.d: Adjust pcrel disassembly. * gas/ms1/errors.exp: Fix target triplet. * gas/ms1/ms1-16-003.d: Adjust pcrel disassembly. * gas/ms1/ms1-16-003.s: Tweak label. * gas/ms1/ms1.exp: Adjust target triplet. Add ms2 test. * gas/ms1/ms2.d, gas/ms1/ms2.s: New. * gas/ms1/relocs.d: Adjust expected machine name and pcrel disassembly. * gas/ms1/relocs.exp: Adjust target triplet. include: Add ms2. * elf/ms1.h (EF_MS1_CPU_MS2): New. opcodes: Add ms2. * ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h: Regenerated. --- bfd/ChangeLog | 13 +++ bfd/archures.c | 1 + bfd/bfd-in2.h | 4 + bfd/cpu-ms1.c | 16 +++- bfd/elf32-ms1.c | 31 +++++-- bfd/libbfd.h | 1 + bfd/reloc.c | 4 + cpu/ChangeLog | 22 +++++ cpu/ms1.cpu | 165 +++++++++++++++++++++++++++++++------ cpu/ms1.opc | 40 ++++++++- gas/ChangeLog | 15 ++++ gas/config/tc-ms1.c | 40 ++++++++- gas/doc/Makefile.am | 1 + gas/doc/Makefile.in | 1 + gas/doc/all.texi | 1 + gas/doc/c-ms1.texi | 44 ++++++++++ gas/testsuite/ChangeLog | 13 +++ gas/testsuite/gas/ms1/allinsn.d | 10 +-- gas/testsuite/gas/ms1/errors.exp | 2 +- gas/testsuite/gas/ms1/ms1-16-003.d | 4 +- gas/testsuite/gas/ms1/ms1-16-003.s | 2 +- gas/testsuite/gas/ms1/ms1.exp | 3 +- gas/testsuite/gas/ms1/ms2.d | 18 ++++ gas/testsuite/gas/ms1/ms2.s | 11 +++ gas/testsuite/gas/ms1/relocs.d | 13 +-- gas/testsuite/gas/ms1/relocs.exp | 2 +- include/ChangeLog | 5 ++ include/elf/ms1.h | 1 + opcodes/ChangeLog | 6 ++ opcodes/ms1-asm.c | 50 ++++++++++- opcodes/ms1-desc.c | 108 +++++++++++++++++++----- opcodes/ms1-desc.h | 53 ++++++------ opcodes/ms1-dis.c | 34 +++++++- opcodes/ms1-ibld.c | 135 ++++++++++++++++++++++++++++++ opcodes/ms1-opc.c | 56 +++++++++++++ opcodes/ms1-opc.h | 14 +++- 36 files changed, 838 insertions(+), 101 deletions(-) create mode 100644 gas/doc/c-ms1.texi create mode 100644 gas/testsuite/gas/ms1/ms2.d create mode 100644 gas/testsuite/gas/ms1/ms2.s diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 37b9562c2d..d74978eaf8 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,16 @@ +2005-11-08 Nathan Sidwell + + Add ms2 support + * archures.c (bfd_mach_ms2): Define. + * cpu-ms1.c (arch_info_struct): Add ms2 stanza. + * elf32-ms1.c (elf32_ms1_machine): Add ms2 case. + (ms1_elf_merge_private_bfd_data): Remove unused variables. Add + correct merging logic, with workaround. + (ms1_elf_print_private_bfd_data): Add ms2 case. + * reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc. + * libbfd.h: Regenerated. + * bfd-in2.h: Regenerated. + 2005-11-07 Steve Ellcey * warning.m4 (AM_BINUTILS_WARNINGS): Default to empty string diff --git a/bfd/archures.c b/bfd/archures.c index a96771cf8d..561ddfc8ec 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -320,6 +320,7 @@ DESCRIPTION . bfd_arch_ms1, .#define bfd_mach_ms1 1 .#define bfd_mach_mrisc2 2 +.#define bfd_mach_ms2 3 . bfd_arch_pj, . bfd_arch_avr, {* Atmel AVR microcontrollers. *} .#define bfd_mach_avr1 1 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 7afe43725a..d8570866fc 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1908,6 +1908,7 @@ enum bfd_architecture bfd_arch_ms1, #define bfd_mach_ms1 1 #define bfd_mach_mrisc2 2 +#define bfd_mach_ms2 3 bfd_arch_pj, bfd_arch_avr, /* Atmel AVR microcontrollers. */ #define bfd_mach_avr1 1 @@ -3970,6 +3971,9 @@ This is the 5 bits of a value. */ /* Morpho MS1 - Used to tell the linker which vtable entries are used. */ BFD_RELOC_MS1_GNU_VTENTRY, +/* Morpho MS1 - 8 bit immediate relocation. */ + BFD_RELOC_MS1_PCINSN8, + /* msp430 specific relocation codes */ BFD_RELOC_MSP430_10_PCREL, BFD_RELOC_MSP430_16_PCREL, diff --git a/bfd/cpu-ms1.c b/bfd/cpu-ms1.c index 1a0a726e30..18d75a0ce3 100644 --- a/bfd/cpu-ms1.c +++ b/bfd/cpu-ms1.c @@ -35,8 +35,22 @@ const bfd_arch_info_type arch_info_struct[] = FALSE, /* The default ? */ bfd_default_compatible, /* Architecture comparison fn. */ bfd_default_scan, /* String to architecture convert fn. */ + &arch_info_struct[1] /* Next in list. */ +}, +{ + 32, /* Bits per word - not really true. */ + 32, /* Bits per address. */ + 8, /* Bits per byte. */ + bfd_arch_ms1, /* Architecture. */ + bfd_mach_ms2, /* Machine. */ + "ms1", /* Architecture name. */ + "ms2", /* Printable name. */ + 1, /* Section align power. */ + FALSE, /* The default ? */ + bfd_default_compatible, /* Architecture comparison fn. */ + bfd_default_scan, /* String to architecture convert fn. */ NULL /* Next in list. */ -} +}, }; const bfd_arch_info_type bfd_ms1_arch = diff --git a/bfd/elf32-ms1.c b/bfd/elf32-ms1.c index 51841e5124..c4ce614210 100644 --- a/bfd/elf32-ms1.c +++ b/bfd/elf32-ms1.c @@ -501,6 +501,7 @@ elf32_ms1_machine (bfd *abfd) { case EF_MS1_CPU_MRISC: return bfd_mach_ms1; case EF_MS1_CPU_MRISC2: return bfd_mach_mrisc2; + case EF_MS1_CPU_MS2: return bfd_mach_ms2; } return bfd_mach_ms1; @@ -548,7 +549,6 @@ ms1_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) { flagword old_flags, new_flags; bfd_boolean error = FALSE; - static bfd * last_ibfd = 0; /* Check if we have the same endianess. */ if (_bfd_generic_verify_endian_match (ibfd, obfd) == FALSE) @@ -569,13 +569,29 @@ ms1_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) ibfd, old_flags, new_flags, elf_flags_init (obfd) ? "yes" : "no"); #endif - elf_flags_init (obfd) = TRUE; - - if ((new_flags & EF_MS1_CPU_MASK) == EF_MS1_CPU_MRISC2) + if (!elf_flags_init (obfd)) + { + old_flags = new_flags; + elf_flags_init (obfd) = TRUE; + } + else if ((new_flags & EF_MS1_CPU_MASK) != (old_flags & EF_MS1_CPU_MASK)) + { + /* CPU has changed. This is invalid, because MRISC, MRISC2 and + MS2 are not subsets of each other. */ + error = 1; + + /* FIXME:However, until the compiler is multilibbed, preventing + mixing breaks the build. So we allow merging and use the + greater CPU value. This is of course unsafe. */ + error = 0; + if ((new_flags & EF_MS1_CPU_MASK) > (old_flags & EF_MS1_CPU_MASK)) + old_flags = ((old_flags & ~EF_MS1_CPU_MASK) + | (new_flags & EF_MS1_CPU_MASK)); + } + if (!error) { - elf_elfheader (obfd)->e_flags = new_flags; - last_ibfd = ibfd; obfd->arch_info = ibfd->arch_info; + elf_elfheader (obfd)->e_flags = old_flags; } return !error; @@ -598,8 +614,9 @@ ms1_elf_print_private_bfd_data (bfd * abfd, void * ptr) switch (flags & EF_MS1_CPU_MASK) { default: - case EF_MS1_CPU_MRISC: fprintf (file, " ms1-16-002"); break; + case EF_MS1_CPU_MRISC: fprintf (file, " ms1-16-002"); break; case EF_MS1_CPU_MRISC2: fprintf (file, " ms1-16-003"); break; + case EF_MS1_CPU_MS2: fprintf (file, " ms2"); break; } fputc ('\n', file); diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 1fc541645c..e05252c949 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1764,6 +1764,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_MS1_LO16", "BFD_RELOC_MS1_GNU_VTINHERIT", "BFD_RELOC_MS1_GNU_VTENTRY", + "BFD_RELOC_MS1_PCINSN8", "BFD_RELOC_MSP430_10_PCREL", "BFD_RELOC_MSP430_16_PCREL", "BFD_RELOC_MSP430_16", diff --git a/bfd/reloc.c b/bfd/reloc.c index ea73d13737..d964f1656c 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -4424,6 +4424,10 @@ ENUM BFD_RELOC_MS1_GNU_VTENTRY ENUMDOC Morpho MS1 - Used to tell the linker which vtable entries are used. +ENUM + BFD_RELOC_MS1_PCINSN8 +ENUMDOC + Morpho MS1 - 8 bit immediate relocation. ENUM BFD_RELOC_MSP430_10_PCREL diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 1fc6255def..e159430def 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,25 @@ +2005-11-08 Nathan Sidwell + + Add ms2 + * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and + model. + (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr, + f-cb2incr, f-rc3): New fields. + (LOOP): New instruction. + (JAL-HAZARD): New hazard. + (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr): + New operands. + (mul, muli, dbnz, iflush): Enable for ms2 + (jal, reti): Has JAL-HAZARD. + (ldctxt, ldfb, stfb): Only ms1. + (fbcb): Only ms1,ms1-003. + (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs, + fbcbincrs, mfbcbincrs): Enable for ms2. + (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns. + * ms1.opc (parse_loopsize): New. + (parse_imm16): hi16/lo16 relocs are applicable to IMM16L. + (print_pcrel): New. + 2005-10-28 Dave Brolley Contribute the following change: diff --git a/cpu/ms1.cpu b/cpu/ms1.cpu index f80690c9d0..441a937334 100644 --- a/cpu/ms1.cpu +++ b/cpu/ms1.cpu @@ -32,7 +32,7 @@ (comment "Morpho Technologies mRISC family") (default-alignment aligned) (insn-lsb0? #t) - (machs ms1 ms1-003) + (machs ms1 ms1-003 ms2) (isas ms1) ) @@ -66,6 +66,14 @@ (word-bitsize 32) ) +(define-cpu + ; cpu names must be distinct from the architecture name and machine names. + (name ms2bf) + (comment "Morpho Technologies mRISC family") + (endian big) + (word-bitsize 32) +) + (define-mach (name ms1) (comment "Morpho Technologies mrisc") @@ -80,6 +88,13 @@ (isas ms1) ) +(define-mach + (name ms2) + (comment "Morpho Technologies ms2") + (cpu ms2bf) + (isas ms1) +) + ; Model descriptions. ; Can probably take the u-exec out. We'll see. @@ -109,10 +124,18 @@ ) ) -; Macros to simplify MACH attribute specification. - -(define-pmacro MACHMS1 (MACH ms1)) -(define-pmacro MACHMS1-003 (MACH ms1-003)) +(define-model + (name ms2) + (comment "Morpho Technologies ms2") + (mach ms2) + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) +) ; FIXME: It might simplify things to separate the execute process from the ; one that updates the PC. @@ -140,6 +163,7 @@ ; f-imm16a: 16 bit immediate value when it's a pc-rel offset. ; f-uu4a: unused 4 bit field. ; f-uu4b: second unsed 4 bit field. +; f-uu1: unused 1 bit field ; f-uu12: unused 12 bit field. ; f-uu16: unused 16 bit field. ; f-uu24: unused 24 bit field. @@ -158,7 +182,9 @@ (dnf f-uu4a "unused 4 bit field" () 19 4) (dnf f-uu4b "unused 4 bit field" () 23 4) (dnf f-uu12 "unused 12 bit field" () 11 12) +(dnf f-uu8 "unused 8 bit field" () 15 8) (dnf f-uu16 "unused 16 bit field" () 15 16) +(dnf f-uu1 "unused 1 bit field" () 7 1) ; The following ifields are used exclusively for the MorphoSys instructions. ; In a few cases, a bit field is used for something in addition to what its @@ -214,6 +240,17 @@ (dnf f-rc2 "rc2" () 6 1) (dnf f-ctxdisp "context displacement" () 5 6) +; additional fields in ms2 +(dnf f-imm16l "loop count" () 23 16) +(df f-loopo "loop offset" () 7 8 UINT + ((value pc) (srl SI value 2)) + ((value pc) (add SI (sll value 2) 8)) + ) +(dnf f-cb1sel "cb1 select" () 25 3) +(dnf f-cb2sel "cb2 select" () 22 3) +(dnf f-cb1incr "cb1 increment" (SIGNED) 19 6) +(dnf f-cb2incr "cb2 increment" (SIGNED) 13 6) +(dnf f-rc3 "row/colum context" () 7 1) ; The following is just for a test (dnf f-msysfrsr2 "sr2 for msys" () 19 4) @@ -237,7 +274,7 @@ (ADD ADDU SUB SUBU MUL - - - AND OR XOR NAND NOR XNOR LDUI - LSL LSR ASR - - - - - - BRLT BRLE BREQ JMP JAL BRNEQ DBNZ - + BRLT BRLE BREQ JMP JAL BRNEQ DBNZ LOOP LDW STW - - - - - - - - - - - - - - EI DI SI RETI BREAK IFLUSH - - @@ -257,7 +294,7 @@ ; insn-imm: bit 24. Immediate operand indicator. (define-normal-insn-enum insn-imm "imm enums" () IMM_ f-imm ; This bit specifies whether and immediate operand will be present. - ; It's 1 if ther is, 0 if there is not. + ; It's 1 if there is, 0 if there is not. (NO YES) ) ;;;;;;;;;;;;;;;; @@ -307,6 +344,13 @@ (comment "insn performs an I/O operation") ) +(define-attr + (for insn) + (type boolean) + (name JAL-HAZARD) + (comment "insn has jal-like hazard") +) + (define-pmacro (define-reg-use-attr regfield) (define-attr (for insn) @@ -375,8 +419,8 @@ (type h-sint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex"))) (define-operand (name imm16z) (comment "immediate value - zero extd") (attrs) (type h-uint) (index f-imm16u) (handlers (parse "imm16") (print "dollarhex"))) -(define-operand (name imm16o) (comment "immediate value") (attrs) - (type h-uint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex"))) +(define-operand (name imm16o) (comment "immediate value") (attrs PCREL-ADDR) + (type h-uint) (index f-imm16s) (handlers (parse "imm16") (print "pcrel"))) ; Operands for MorphoSys Instructions @@ -490,6 +534,24 @@ (define-operand (name fbincr) (comment "fb incr") (attrs) (type h-uint) (index f-fbincr) (handlers (print "dollarhex"))) +; For the ms2 insns +(define-operand (name loopsize) (comment "immediate value") + (attrs (MACH ms2) PCREL-ADDR) + (type h-uint) (index f-loopo) (handlers (parse "loopsize") (print "pcrel"))) +(define-operand (name imm16l) (comment "immediate value") + (attrs (MACH ms2)) + (type h-uint) (index f-imm16l) (handlers (print "dollarhex"))) +(define-operand (name rc3) (comment "rc3") (attrs (MACH ms2)) + (type h-uint) (index f-rc3) (handlers (parse "rc") (print "dollarhex"))) +(define-operand (name cb1sel) (comment "cb1sel") (attrs (MACH ms2)) + (type h-uint) (index f-cb1sel) (handlers (print "dollarhex"))) +(define-operand (name cb2sel) (comment "cb2sel") (attrs (MACH ms2)) + (type h-uint) (index f-cb2sel) (handlers (print "dollarhex"))) +(define-operand (name cb1incr) (comment "cb1incr") (attrs (MACH ms2)) + (type h-sint) (index f-cb1incr) (handlers (print "dollarhex"))) +(define-operand (name cb2incr) (comment "cb2incr") (attrs (MACH ms2)) + (type h-sint) (index f-cb2incr) (handlers (print "dollarhex"))) + ; Probaby won't need most of these. (define-pmacro r0 (reg h-spr #x0)) (define-pmacro r1 (reg h-spr #x01)) @@ -594,7 +656,7 @@ ) (dni mul "MUL DstReg, SrcReg1, SrcReg2" - (MACHMS1-003 AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) + ((MACH ms1-003,ms2) AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) "mul $frdrrr,$frsr1,$frsr2" (+ MSYS_NO OPC_MUL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) (sequence((HI op1) (HI op2)) @@ -612,7 +674,7 @@ ) (dni muli "MULI DstReg, SrcReg1, UnsImm" - (MACHMS1-003 AL-INSN USES-FRDR USES-FRSR1) + ((MACH ms1-003,ms2) AL-INSN USES-FRDR USES-FRSR1) "muli $frdr,$frsr1,#$imm16" (+ MSYS_NO OPC_MUL IMM_YES frsr1 frdr imm16) (sequence((HI op1) (HI op2)) @@ -851,7 +913,7 @@ ) (dni jal "JAL DstReg, SrcReg1" - (BR-INSN DELAY-SLOT BR-INSN USES-FRDR USES-FRSR1) + (BR-INSN DELAY-SLOT BR-INSN USES-FRDR USES-FRSR1 JAL-HAZARD) "jal $frdrrr,$frsr1" (+ MSYS_NO OPC_JAL IMM_NO frsr1 (f-uu4a 0) frdrrr (f-uu12 0)) (sequence() @@ -867,7 +929,7 @@ ) (dni dbnz "DBNZ SrcReg1, label" - (MACHMS1-003 BR-INSN DELAY-SLOT USES-FRSR1) + ((MACH ms1-003,ms2) BR-INSN DELAY-SLOT USES-FRSR1) "dbnz $frsr1,$imm16o" (+ MSYS_NO OPC_DBNZ IMM_YES frsr1 (f-uu4a 0) imm16o) (sequence() @@ -913,7 +975,7 @@ ) (dni reti "RETI SrcReg1" - (DELAY-SLOT BR-INSN USES-FRSR1) + (DELAY-SLOT BR-INSN USES-FRSR1 JAL-HAZARD) "reti $frsr1" (+ MSYS_NO OPC_RETI IMM_NO frsr1 (f-uu4a 0) (f-uu16 0)) (sequence() @@ -962,7 +1024,7 @@ ; Cache Flush Instruction (dni iflush "IFLUSH" - (MACHMS1-003) + ((MACH ms1-003,ms2)) "iflush" (+ MSYS_NO OPC_IFLUSH (f-imm 0) (f-uu24 0)) (nop) @@ -972,7 +1034,7 @@ ; MorphoSys Instructions (dni ldctxt "LDCTXT SRC1, SRC2, r/c, r/c#, context#" - () + ((MACH ms1)) "ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum" (+ MSYS_YES MSOPC_LDCTXT (f-uu-2-25 0) frsr1 frsr2 rc rcnum (f-uu-3-11 0) contnum ) @@ -981,7 +1043,7 @@ ) (dni ldfb "LDFB SRC1, byte#" - () + ((MACH ms1)) "ldfb $frsr1,$frsr2,#$imm16z" (+ MSYS_YES MSOPC_LDFB (f-uu-2-25 0) frsr1 frsr2 imm16z) (nop) @@ -989,7 +1051,7 @@ ) (dni stfb "STFB SRC1, SRC2, byte " - () + ((MACH ms1)) "stfb $frsr1,$frsr2,#$imm16z" (+ MSYS_YES MSOPC_STFB (f-uu-2-25 0) frsr1 frsr2 imm16z) (nop) @@ -997,7 +1059,7 @@ ) (dni fbcb "FBCB SRC1, RT/BR1/BR2/CS, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp" - () + ((MACH ms1,ms1-003)) "fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" (+ MSYS_YES MSOPC_FBCB rbbc frsr1 ball brc (f-uu-4-15 0) rc cbrb cell dup ctxdisp) (nop) @@ -1176,7 +1238,7 @@ ;; Issue 66262: The documenatation gives the wrong order for ;; the arguments to the WFBINC instruction. (dni wfbinc "WFBINC type, ccb/rcb, incr, all, c/r, length, rca_row, word, dup, ctxt_disp" - (MACHMS1-003) + ((MACH ms1-003,ms2)) "wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp" (+ MSYS_YES MSOPC_WFBINC rda wr fbincr ball colnum length rownum1 rownum2 dup ctxdisp) (nop) @@ -1184,7 +1246,7 @@ ) (dni mwfbinc "MWFBINC mreg, type, ccb/rcb, incr, length, rca_row, word, dup, ctxt_disp" - (MACHMS1-003) + ((MACH ms1-003,ms2)) "mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp" (+ MSYS_YES MSOPC_MWFBINC rda wr fbincr frsr2 length rownum1 rownum2 dup ctxdisp) (nop) @@ -1192,7 +1254,7 @@ ) (dni wfbincr "WFBINCR ireg, type, ccb/rcb, all, c/r, length, rca_row, word, dup, ctxt_disp" - (MACHMS1-003) + ((MACH ms1-003,ms2)) "wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp" (+ MSYS_YES MSOPC_WFBINCR rda wr frsr1 ball colnum length rownum1 rownum2 dup ctxdisp) (nop) @@ -1200,7 +1262,7 @@ ) (dni mwfbincr "MWFBINCR ireg, mreg, type, ccb/rcb, length, rca_row, word, dup, ctxt_disp" - (MACHMS1-003) + ((MACH ms1-003,ms2)) "mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp" (+ MSYS_YES MSOPC_MWFBINCR rda wr frsr1 frsr2 length rownum1 rownum2 dup ctxdisp) (nop) @@ -1208,7 +1270,7 @@ ) (dni fbcbincs "FBCBINCS perm, all, c/r, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp" - (MACHMS1-003) + ((MACH ms1-003,ms2)) "fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp" (+ MSYS_YES MSOPC_FBCBINCS perm a23 cr cbs incr ccb cdb rownum2 dup ctxdisp) (nop) @@ -1216,7 +1278,7 @@ ) (dni mfbcbincs "MFBCBINCS ireg, perm, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp" - (MACHMS1-003) + ((MACH ms1-003,ms2)) "mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp" (+ MSYS_YES MSOPC_MFBCBINCS perm frsr1 cbs incr ccb cdb rownum2 dup ctxdisp) (nop) @@ -1224,7 +1286,7 @@ ) (dni fbcbincrs "FBCBINCRS ireg, perm, all, c/r, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp" - (MACHMS1-003) + ((MACH ms1-003,ms2)) "fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp" (+ MSYS_YES MSOPC_FBCBINCRS perm frsr1 ball colnum (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp) (nop) @@ -1232,9 +1294,58 @@ ) (dni mfbcbincrs "MFBCBINCRS ireg, mreg, perm, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp" - (MACHMS1-003) + ((MACH ms1-003,ms2)) "mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp" (+ MSYS_YES MSOPC_MFBCBINCRS perm frsr1 frsr2 (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp) (nop) () ) + +; MS2 instructions +(dni loop "LOOP SrcReg1, label" + ((MACH ms2) DELAY-SLOT USES-FRSR1) + "loop $frsr1,$loopsize" + (+ MSYS_NO OPC_LOOP IMM_NO frsr1 (f-uu4a 0) (f-uu8 0) loopsize) + (nop) ;; to be filled in + () +) + +(dni loopi "LOOPI niter, label" + ((MACH ms2) DELAY-SLOT) + "loopi #$imm16l,$loopsize" + (+ MSYS_NO OPC_LOOP IMM_YES imm16l loopsize) + (nop) ;; to be filled in + () +) + +(dni dfbc "dfbc cb1sel,cb2sel,cb1inc,cb2inc,dr/c,cr/c,ctxdisp" + ((MACH ms2)) + "dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp" + (+ MSYS_YES MSOPC_LDCTXT cb1sel cb2sel cb1incr cb2incr rc3 rc2 ctxdisp) + (nop) + () +) + +(dni dwfb "dwfb cb1sel,cb2sel,cb1inc,cb2inc,cr/c,ctxdisp" + ((MACH ms2)) + "dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp" + (+ MSYS_YES MSOPC_LDFB cb1sel cb2sel cb1incr cb2incr (f-uu1 0) rc2 ctxdisp) + (nop) + () +) + +(dni fbwfb "fbwfb cb1sel,cb2sel,cb1inc,cb2inc,r0/1,cr/c,ctxdisp" + ((MACH ms2)) + "fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp" + (+ MSYS_YES MSOPC_STFB cb1sel cb2sel cb1incr cb2incr rc3 rc2 ctxdisp) + (nop) + () +) + +(dni dfbr "dfbr cb1sel,cb2sel,reg,W/O1,W/O2,mode,cr/c,ctxdisp" + ((MACH ms2) USES-FRSR2) + "dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp" + (+ MSYS_YES MSOPC_FBCB cb1sel cb2sel frsr2 length rownum1 rownum2 rc2 ctxdisp) + (nop) + () +) diff --git a/cpu/ms1.opc b/cpu/ms1.opc index 3655f14d45..e3b32db7b9 100644 --- a/cpu/ms1.opc +++ b/cpu/ms1.opc @@ -101,6 +101,31 @@ signed_out_of_bounds (long val) } static const char * +parse_loopsize (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + void *arg) +{ + signed long * valuep = (signed long *) arg; + const char *errmsg; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Is it a control transfer instructions? */ + if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_LOOPSIZE) + { + code = BFD_RELOC_MS1_PCINSN8; + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + *valuep = value; + return errmsg; + } + + abort (); +} + +static const char * parse_imm16 (CGEN_CPU_DESC cd, const char **strp, int opindex, @@ -129,7 +154,9 @@ parse_imm16 (CGEN_CPU_DESC cd, /* If it's not a control transfer instruction, then we have to check for %OP relocating operators. */ - if (strncmp (*strp, "%hi16", 5) == 0) + if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16L) + ; + else if (strncmp (*strp, "%hi16", 5) == 0) { *strp += 5; code = BFD_RELOC_HI16; @@ -411,6 +438,7 @@ parse_type (CGEN_CPU_DESC cd, /* -- dis.c */ static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int); +static void print_pcrel (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int); static void print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, @@ -428,6 +456,16 @@ print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, print_normal (cd, dis_info, value, attrs, pc, length); } +static void +print_pcrel (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_address (cd, dis_info, value + pc, attrs, pc, length); +} /* -- */ diff --git a/gas/ChangeLog b/gas/ChangeLog index 4556e03896..cfbd5198f7 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,18 @@ +2005-11-08 Nathan Sidwell + + Add ms2 support. + * config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1. + (ms1_architectures): Add ms2. + (md_parse_option): Add ms2. + (md_show_usage): Add ms2. + (md_assemble): Add JAL_HAZARD detection logic. + (md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case. + * doc/c-ms1.texi: New. + * doc/all.texi: Add MS1. + * doc/Makefile.am (CPU_DOCS): Add c-ms1.texi. + * doc/Makefile.in: Rebuilt. + * doc/Makefile: Rebuilt. + 2005-11-07 Steve Ellcey * configure: Regenerate after modifying bfd/warning.m4. diff --git a/gas/config/tc-ms1.c b/gas/config/tc-ms1.c index e459bc8431..7e2e685029 100644 --- a/gas/config/tc-ms1.c +++ b/gas/config/tc-ms1.c @@ -84,7 +84,7 @@ const char * md_shortopts = ""; /* Mach selected from command line. */ static int ms1_mach = bfd_mach_ms1; -static unsigned ms1_mach_bitmask = 0; +static unsigned ms1_mach_bitmask = 1 << MACH_MS1; /* Flags to set in the elf header */ static flagword ms1_flags = EF_MS1_CPU_MRISC; @@ -94,7 +94,8 @@ enum ms1_architectures { ms1_64_001, ms1_16_002, - ms1_16_003 + ms1_16_003, + ms2 }; /* MS1 architecture we are using for this output file. */ @@ -127,6 +128,13 @@ md_parse_option (int c ATTRIBUTE_UNUSED, char * arg) ms1_mach_bitmask = 1 << MACH_MS1_003; ms1_arch = ms1_16_003; } + else if (strcasecmp (arg, "MS2") == 0) + { + ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MS2; + ms1_mach = bfd_mach_mrisc2; + ms1_mach_bitmask = 1 << MACH_MS2; + ms1_arch = ms2; + } case OPTION_NO_SCHED_REST: no_scheduling_restrictions = 1; break; @@ -145,6 +153,7 @@ md_show_usage (FILE * stream) fprintf (stream, _(" -march=ms1-64-001 allow ms1-64-001 instructions (default) \n")); fprintf (stream, _(" -march=ms1-16-002 allow ms1-16-002 instructions \n")); fprintf (stream, _(" -march=ms1-16-003 allow ms1-16-003 instructions \n")); + fprintf (stream, _(" -march=ms2 allow ms2 instructions \n")); fprintf (stream, _(" -nosched disable scheduling restrictions \n")); } @@ -176,6 +185,7 @@ void md_assemble (char * str) { static long delayed_load_register = 0; + static long prev_delayed_load_register = 0; static int last_insn_had_delay_slot = 0; static int last_insn_in_noncond_delay_slot = 0; static int last_insn_has_load_delay = 0; @@ -241,6 +251,24 @@ md_assemble (char * str) insn.fields.f_sr2); } + /* Detect JAL/RETI hazard */ + if (ms1_mach == ms2 + && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_JAL_HAZARD)) + { + if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1) + && insn.fields.f_sr1 == delayed_load_register) + || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2) + && insn.fields.f_sr2 == delayed_load_register)) + as_warn (_("operand references R%ld of previous instrutcion."), + delayed_load_register); + else if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1) + && insn.fields.f_sr1 == prev_delayed_load_register) + || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2) + && insn.fields.f_sr2 == prev_delayed_load_register)) + as_warn (_("operand references R%ld of instructcion before previous."), + prev_delayed_load_register); + } + /* Detect data dependency between conditional branch instruction and an immediately preceding arithmetic or logical instruction. */ if (last_insn_was_arithmetic_or_logic @@ -287,6 +315,8 @@ md_assemble (char * str) CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN) && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2); + prev_delayed_load_register = delayed_load_register; + if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDR)) delayed_load_register = insn.fields.f_dr; else if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDRRR)) @@ -381,6 +411,12 @@ md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED, result = fixP->fx_cgen.opinfo; fixP->fx_no_overflow = 1; break; + case MS1_OPERAND_LOOPSIZE: + result = BFD_RELOC_MS1_PCINSN8; + fixP->fx_pcrel = 1; + /* Adjust for the delay slot, which is not part of the loop */ + fixP->fx_offset -= 8; + break; default: result = BFD_RELOC_NONE; break; diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am index 14770d51a4..a2785d4c3c 100644 --- a/gas/doc/Makefile.am +++ b/gas/doc/Makefile.am @@ -42,6 +42,7 @@ CPU_DOCS = \ c-m68k.texi \ c-mips.texi \ c-mmix.texi \ + c-ms1.texi \ c-msp430.texi \ c-ns32k.texi \ c-pdp11.texi \ diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in index d8d4419576..0fae5271bb 100644 --- a/gas/doc/Makefile.in +++ b/gas/doc/Makefile.in @@ -234,6 +234,7 @@ CPU_DOCS = \ c-m68k.texi \ c-mips.texi \ c-mmix.texi \ + c-ms1.texi \ c-msp430.texi \ c-ns32k.texi \ c-pdp11.texi \ diff --git a/gas/doc/all.texi b/gas/doc/all.texi index c10ec0889d..2476b2e526 100644 --- a/gas/doc/all.texi +++ b/gas/doc/all.texi @@ -48,6 +48,7 @@ @set MCORE @set MIPS @set MMIX +@set MS1 @set MSP430 @set PDP11 @set PJ diff --git a/gas/doc/c-ms1.texi b/gas/doc/c-ms1.texi new file mode 100644 index 0000000000..854d411952 --- /dev/null +++ b/gas/doc/c-ms1.texi @@ -0,0 +1,44 @@ +@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 +@c Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + +@ifset GENERIC +@page +@node MS1-Dependent +@chapter MS1 Dependent Features +@end ifset + +@ifclear GENERIC +@node Machine Dependencies +@chapter MS1 Dependent Features +@end ifclear + +@cindex MS1 support +@menu +* MS1 Options:: Options +@end menu + +@node MS1 Options +@section Options +@cindex MS1 options (none) +@cindex options for MS1 (none) + +@table @code + +@cindex @code{-march=} command line option, MS1 +@item -march=@var{processor} +This option specifies the target processor. The assembler will issue an +error message if an attempt is made to assemble an instruction which +will not execute on the target processor. The following processor names are +recognized: +@code{ms1-64-001}, +@code{ms1-16-002}, +@code{ms1-16-003}, +and @code{ms2}. + +@cindex @code{-nosched} command line option, MS1 +@item -nosched +This option disables scheduling restriction checking. + +@end table diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index d9a47c5ea5..8bd4ffcfa8 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2005-11-08 Nathan Sidwell + + Add ms2. + * gas/ms1/allinsn.d: Adjust pcrel disassembly. + * gas/ms1/errors.exp: Fix target triplet. + * gas/ms1/ms1-16-003.d: Adjust pcrel disassembly. + * gas/ms1/ms1-16-003.s: Tweak label. + * gas/ms1/ms1.exp: Adjust target triplet. Add ms2 test. + * gas/ms1/ms2.d, gas/ms1/ms2.s: New. + * gas/ms1/relocs.d: Adjust expected machine name and pcrel + disassembly. + * gas/ms1/relocs.exp: Adjust target triplet. + 2005-11-07 Jan Beulich * gas/all/redef2.[sd]: New. diff --git a/gas/testsuite/gas/ms1/allinsn.d b/gas/testsuite/gas/ms1/allinsn.d index d992c58744..03db93d139 100644 --- a/gas/testsuite/gas/ms1/allinsn.d +++ b/gas/testsuite/gas/ms1/allinsn.d @@ -88,16 +88,16 @@ Disassembly of section .text: 68: 25 00 00 00 asri R0,R0,#\$0 0000006c : - 6c: 31 00 00 00 brlt R0,R0,\$0 + 6c: 31 00 00 00 brlt R0,R0,6c 00000070 : - 70: 33 00 00 00 brle R0,R0,\$0 + 70: 33 00 00 00 brle R0,R0,70 00000074 : - 74: 35 00 00 00 breq R0,R0,\$0 + 74: 35 00 00 00 breq R0,R0,74 00000078 : - 78: 37 00 00 00 jmp \$0 + 78: 37 00 00 00 jmp 78 0000007c : 7c: 38 00 00 00 jal R0,R0 @@ -121,7 +121,7 @@ Disassembly of section .text: 94: 64 00 00 00 si R0 00000098 : - 98: 3b 00 00 00 brne R0,R0,\$0 + 98: 3b 00 00 00 brne R0,R0,98 0000009c : 9c: 68 00 00 00 break diff --git a/gas/testsuite/gas/ms1/errors.exp b/gas/testsuite/gas/ms1/errors.exp index 90a8976c5f..dd47d437ce 100644 --- a/gas/testsuite/gas/ms1/errors.exp +++ b/gas/testsuite/gas/ms1/errors.exp @@ -27,7 +27,7 @@ proc mrisc1_error_test { file testname {warnpattern ""} } { } } -if [istarget mrisc1*-*-*] { +if [istarget ms1-*-*] { foreach file [glob -nocomplain -- $srcdir/$subdir/bad*.s] { set file [file tail $file] switch -- $file { diff --git a/gas/testsuite/gas/ms1/ms1-16-003.d b/gas/testsuite/gas/ms1/ms1-16-003.d index 0233d851d4..f8556962f8 100644 --- a/gas/testsuite/gas/ms1/ms1-16-003.d +++ b/gas/testsuite/gas/ms1/ms1-16-003.d @@ -12,8 +12,8 @@ Disassembly of section .text: 4: 08 00 00 00 mul R0,R0,R0 00000008 : 8: 09 00 00 00 muli R0,R0,#\$0 -0000000c : - c: 3d 00 00 00 dbnz R0,\$0 +0000000c : + c: 3d 00 00 00 dbnz R0,c [ ]*c: R_MS1_PC16 dbnz 00000010 : 10: f0 00 00 00 fbcbincs #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 diff --git a/gas/testsuite/gas/ms1/ms1-16-003.s b/gas/testsuite/gas/ms1/ms1-16-003.s index ec1dd7b90e..516fff5717 100644 --- a/gas/testsuite/gas/ms1/ms1-16-003.s +++ b/gas/testsuite/gas/ms1/ms1-16-003.s @@ -12,7 +12,7 @@ muli: muli R0, R0, #0 .global dbnz -dbnz: +dbnz_: dbnz r0, dbnz .global fbcbincs diff --git a/gas/testsuite/gas/ms1/ms1.exp b/gas/testsuite/gas/ms1/ms1.exp index 49aea8181b..1960f0d5b6 100644 --- a/gas/testsuite/gas/ms1/ms1.exp +++ b/gas/testsuite/gas/ms1/ms1.exp @@ -1,10 +1,11 @@ # MRISC1 assembler testsuite. -if { [istarget mrisc1*-*-*] || [istarget ms1-*-*]} then { +if [istarget ms1*-*-*] { # run_dump_test "allinsn" run_dump_test "misc" run_dump_test "msys" run_dump_test "ms1-16-003" + run_dump_test "ms2" # } diff --git a/gas/testsuite/gas/ms1/ms2.d b/gas/testsuite/gas/ms1/ms2.d new file mode 100644 index 0000000000..8771052214 --- /dev/null +++ b/gas/testsuite/gas/ms1/ms2.d @@ -0,0 +1,18 @@ +#as: -march=ms2 +#objdump: -dr +#name: ms2 + +.*: +file format .* + +Disassembly of section .text: + +00000000 : + 0: 3e 10 00 05 loop R1,1c