From 866c5c18602dc6c257bf681a5d8dcd852e8f0e19 Mon Sep 17 00:00:00 2001 From: Richard Smith Date: Thu, 5 Jan 2017 03:13:10 +0000 Subject: [PATCH] Revert r291025 ("AMDGPU: Remove unneccessary intermediate vector") This caused buildbot failures due to returning ArrayRefs referencing local (temporary) objects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291067 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 40 +++++++++++-------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 092feaf4ea5..a6c31629e7c 100644 --- a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -822,7 +822,6 @@ public: bool isForcedVOP3() const { return ForcedEncodingSize == 64; } bool isForcedDPP() const { return ForcedDPP; } bool isForcedSDWA() const { return ForcedSDWA; } - ArrayRef getMatchedVariants() const; std::unique_ptr parseRegister(); bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; @@ -1631,34 +1630,31 @@ unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) { return Match_Success; } -// What asm variants we should check -ArrayRef AMDGPUAsmParser::getMatchedVariants() const { - if (getForcedEncodingSize() == 32) - return {AMDGPUAsmVariants::DEFAULT}; - - if (isForcedVOP3()) - return {AMDGPUAsmVariants::VOP3}; - - if (isForcedSDWA()) - return {AMDGPUAsmVariants::SDWA}; - - if (isForcedDPP()) - return {AMDGPUAsmVariants::DPP}; - - return {AMDGPUAsmVariants::DEFAULT, - AMDGPUAsmVariants::VOP3, - AMDGPUAsmVariants::SDWA, - AMDGPUAsmVariants::DPP}; -} - bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) { + // What asm variants we should check + std::vector MatchedVariants; + if (getForcedEncodingSize() == 32) { + MatchedVariants = {AMDGPUAsmVariants::DEFAULT}; + } else if (isForcedVOP3()) { + MatchedVariants = {AMDGPUAsmVariants::VOP3}; + } else if (isForcedSDWA()) { + MatchedVariants = {AMDGPUAsmVariants::SDWA}; + } else if (isForcedDPP()) { + MatchedVariants = {AMDGPUAsmVariants::DPP}; + } else { + MatchedVariants = {AMDGPUAsmVariants::DEFAULT, + AMDGPUAsmVariants::VOP3, + AMDGPUAsmVariants::SDWA, + AMDGPUAsmVariants::DPP}; + } + MCInst Inst; unsigned Result = Match_Success; - for (auto Variant : getMatchedVariants()) { + for (auto Variant : MatchedVariants) { uint64_t EI; auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm, Variant); -- 2.11.0