From 8711de225b0b4289c51354ea19e191d7ead9653b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 9 Jul 2016 18:11:15 +0000 Subject: [PATCH] AMDGPU: Move R600 only pieces into R600 classes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274979 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPUFrameLowering.h | 5 --- lib/Target/AMDGPU/AMDGPUInstrInfo.cpp | 57 -------------------------------- lib/Target/AMDGPU/AMDGPUInstrInfo.h | 18 ---------- lib/Target/AMDGPU/AMDGPURegisterInfo.cpp | 11 ------ lib/Target/AMDGPU/AMDGPURegisterInfo.h | 6 ---- lib/Target/AMDGPU/R600InstrInfo.cpp | 57 ++++++++++++++++++++++++++++++++ lib/Target/AMDGPU/R600InstrInfo.h | 12 ++++++- lib/Target/AMDGPU/R600RegisterInfo.cpp | 7 ++++ lib/Target/AMDGPU/R600RegisterInfo.h | 7 +++- lib/Target/AMDGPU/SIInstrInfo.cpp | 8 ----- lib/Target/AMDGPU/SIInstrInfo.h | 2 -- 11 files changed, 81 insertions(+), 109 deletions(-) diff --git a/lib/Target/AMDGPU/AMDGPUFrameLowering.h b/lib/Target/AMDGPU/AMDGPUFrameLowering.h index 44196e2db49..513848a1d88 100644 --- a/lib/Target/AMDGPU/AMDGPUFrameLowering.h +++ b/lib/Target/AMDGPU/AMDGPUFrameLowering.h @@ -36,11 +36,6 @@ public: int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override; - const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries) const override { - NumEntries = 0; - return nullptr; - } - bool hasFP(const MachineFunction &MF) const override { return false; } diff --git a/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp b/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp index e4f9634b989..9a00ecb24eb 100644 --- a/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp +++ b/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp @@ -59,63 +59,6 @@ bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, return (NumLoads <= 16 && (Offset1 - Offset0) < 64); } -int AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const { - const MachineRegisterInfo &MRI = MF.getRegInfo(); - const MachineFrameInfo *MFI = MF.getFrameInfo(); - int Offset = -1; - - if (MFI->getNumObjects() == 0) { - return -1; - } - - if (MRI.livein_empty()) { - return 0; - } - - const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass(); - for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), - LE = MRI.livein_end(); - LI != LE; ++LI) { - unsigned Reg = LI->first; - if (TargetRegisterInfo::isVirtualRegister(Reg) || - !IndirectRC->contains(Reg)) - continue; - - unsigned RegIndex; - unsigned RegEnd; - for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd; - ++RegIndex) { - if (IndirectRC->getRegister(RegIndex) == Reg) - break; - } - Offset = std::max(Offset, (int)RegIndex); - } - - return Offset + 1; -} - -int AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const { - int Offset = 0; - const MachineFrameInfo *MFI = MF.getFrameInfo(); - - // Variable sized objects are not supported - if (MFI->hasVarSizedObjects()) { - return -1; - } - - if (MFI->getNumObjects() == 0) { - return -1; - } - - const AMDGPUSubtarget &ST = MF.getSubtarget(); - const AMDGPUFrameLowering *TFL = ST.getFrameLowering(); - - unsigned IgnoredFrameReg; - Offset = TFL->getFrameIndexReference(MF, -1, IgnoredFrameReg); - - return getIndirectIndexBegin(MF) + Offset; -} - int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const { switch (Channels) { default: return Opcode; diff --git a/lib/Target/AMDGPU/AMDGPUInstrInfo.h b/lib/Target/AMDGPU/AMDGPUInstrInfo.h index 6203e575bfa..a59eafadeb9 100644 --- a/lib/Target/AMDGPU/AMDGPUInstrInfo.h +++ b/lib/Target/AMDGPU/AMDGPUInstrInfo.h @@ -44,14 +44,6 @@ private: public: explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st); - /// \returns the smallest register index that will be accessed by an indirect - /// read or write or -1 if indirect addressing is not used by this program. - int getIndirectIndexBegin(const MachineFunction &MF) const; - - /// \returns the largest register index that will be accessed by an indirect - /// read or write or -1 if indirect addressing is not used by this program. - int getIndirectIndexEnd(const MachineFunction &MF) const; - bool enableClusterLoads() const override; bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, @@ -63,16 +55,6 @@ public: /// not exist. If Opcode is not a pseudo instruction, this is identity. int pseudoToMCOpcode(int Opcode) const; -//===---------------------------------------------------------------------===// -// Pure virtual funtions to be implemented by sub-classes. -//===---------------------------------------------------------------------===// - - /// \returns The register class to be used for loading and storing values - /// from an "Indirect Address" . - virtual const TargetRegisterClass *getIndirectAddrRegClass() const { - llvm_unreachable("getIndirectAddrRegClass() not implemented"); - } - /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the /// equivalent opcode that writes \p Channels Channels. int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const; diff --git a/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp b/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp index 2157c8faa1d..941f2d8a468 100644 --- a/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp +++ b/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp @@ -32,13 +32,6 @@ const MCPhysReg *AMDGPURegisterInfo::getCalleeSavedRegs( return &CalleeSavedReg; } -void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, - int SPAdj, - unsigned FIOperandNum, - RegScavenger *RS) const { - llvm_unreachable("Subroutines not supported yet"); -} - unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const { return AMDGPU::NoRegister; } @@ -55,9 +48,5 @@ unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const { return SubRegs[Channel]; } -unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const { - return getSubRegFromChannel(IndirectIndex); -} - #define GET_REGINFO_TARGET_DESC #include "AMDGPUGenRegisterInfo.inc" diff --git a/lib/Target/AMDGPU/AMDGPURegisterInfo.h b/lib/Target/AMDGPU/AMDGPURegisterInfo.h index e780ca0ad0d..ef51aad95dc 100644 --- a/lib/Target/AMDGPU/AMDGPURegisterInfo.h +++ b/lib/Target/AMDGPU/AMDGPURegisterInfo.h @@ -16,7 +16,6 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H -#include "llvm/ADT/BitVector.h" #include "llvm/Target/TargetRegisterInfo.h" #define GET_REGINFO_HEADER @@ -36,12 +35,7 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo { unsigned getSubRegFromChannel(unsigned Channel) const; const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override; - void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, - unsigned FIOperandNum, - RegScavenger *RS) const override; unsigned getFrameRegister(const MachineFunction &MF) const override; - - unsigned getIndirectSubReg(unsigned IndirectIndex) const; }; } // End namespace llvm diff --git a/lib/Target/AMDGPU/R600InstrInfo.cpp b/lib/Target/AMDGPU/R600InstrInfo.cpp index fd12ac95f34..72a81131695 100644 --- a/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -1197,6 +1197,63 @@ MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB, return Mov; } +int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const { + const MachineRegisterInfo &MRI = MF.getRegInfo(); + const MachineFrameInfo *MFI = MF.getFrameInfo(); + int Offset = -1; + + if (MFI->getNumObjects() == 0) { + return -1; + } + + if (MRI.livein_empty()) { + return 0; + } + + const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass(); + for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), + LE = MRI.livein_end(); + LI != LE; ++LI) { + unsigned Reg = LI->first; + if (TargetRegisterInfo::isVirtualRegister(Reg) || + !IndirectRC->contains(Reg)) + continue; + + unsigned RegIndex; + unsigned RegEnd; + for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd; + ++RegIndex) { + if (IndirectRC->getRegister(RegIndex) == Reg) + break; + } + Offset = std::max(Offset, (int)RegIndex); + } + + return Offset + 1; +} + +int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const { + int Offset = 0; + const MachineFrameInfo *MFI = MF.getFrameInfo(); + + // Variable sized objects are not supported + if (MFI->hasVarSizedObjects()) { + return -1; + } + + if (MFI->getNumObjects() == 0) { + return -1; + } + + const R600Subtarget &ST = MF.getSubtarget(); + const R600FrameLowering *TFL = ST.getFrameLowering(); + + unsigned IgnoredFrameReg; + Offset = TFL->getFrameIndexReference(MF, -1, IgnoredFrameReg); + + return getIndirectIndexBegin(MF) + Offset; +} + unsigned R600InstrInfo::getMaxAlusPerClause() const { return 115; } diff --git a/lib/Target/AMDGPU/R600InstrInfo.h b/lib/Target/AMDGPU/R600InstrInfo.h index 1e53d872bbf..fa1f49ec570 100644 --- a/lib/Target/AMDGPU/R600InstrInfo.h +++ b/lib/Target/AMDGPU/R600InstrInfo.h @@ -226,7 +226,17 @@ public: unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const; - const TargetRegisterClass *getIndirectAddrRegClass() const override; + /// \returns The register class to be used for loading and storing values + /// from an "Indirect Address" . + const TargetRegisterClass *getIndirectAddrRegClass() const; + + /// \returns the smallest register index that will be accessed by an indirect + /// read or write or -1 if indirect addressing is not used by this program. + int getIndirectIndexBegin(const MachineFunction &MF) const; + + /// \returns the largest register index that will be accessed by an indirect + /// read or write or -1 if indirect addressing is not used by this program. + int getIndirectIndexEnd(const MachineFunction &MF) const; /// \brief Build instruction(s) for an indirect register write. /// diff --git a/lib/Target/AMDGPU/R600RegisterInfo.cpp b/lib/Target/AMDGPU/R600RegisterInfo.cpp index 4c3a3f730fe..dfdc602b80c 100644 --- a/lib/Target/AMDGPU/R600RegisterInfo.cpp +++ b/lib/Target/AMDGPU/R600RegisterInfo.cpp @@ -89,3 +89,10 @@ bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const { return true; } } + +void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, + int SPAdj, + unsigned FIOperandNum, + RegScavenger *RS) const { + llvm_unreachable("Subroutines not supported yet"); +} diff --git a/lib/Target/AMDGPU/R600RegisterInfo.h b/lib/Target/AMDGPU/R600RegisterInfo.h index c1a1402ebe1..9dfb3106c6c 100644 --- a/lib/Target/AMDGPU/R600RegisterInfo.h +++ b/lib/Target/AMDGPU/R600RegisterInfo.h @@ -40,8 +40,13 @@ struct R600RegisterInfo final : public AMDGPURegisterInfo { const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const override; - // \returns true if \p Reg can be defined in one ALU caluse and used in another. + // \returns true if \p Reg can be defined in one ALU clause and used in + // another. bool isPhysRegLiveAcrossClauses(unsigned Reg) const; + + void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, + unsigned FIOperandNum, + RegScavenger *RS = nullptr) const override; }; } // End namespace llvm diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp index 798ff08bef1..8898a305669 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2675,14 +2675,6 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const { } } -//===----------------------------------------------------------------------===// -// Indirect addressing callbacks -//===----------------------------------------------------------------------===// - -const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const { - return &AMDGPU::VGPR_32RegClass; -} - void SIInstrInfo::lowerScalarAbs(SmallVectorImpl &Worklist, MachineInstr &Inst) const { MachineBasicBlock &MBB = *Inst.getParent(); diff --git a/lib/Target/AMDGPU/SIInstrInfo.h b/lib/Target/AMDGPU/SIInstrInfo.h index 1d2c0ba8f56..9a72ac19d06 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.h +++ b/lib/Target/AMDGPU/SIInstrInfo.h @@ -466,8 +466,6 @@ public: /// VALU if necessary. void moveToVALU(MachineInstr &MI) const; - const TargetRegisterClass *getIndirectAddrRegClass() const override; - void insertWaitStates(MachineBasicBlock &MBB,MachineBasicBlock::iterator MI, int Count) const; -- 2.11.0