From 8a83f71301fdf0e2cea8ecdf413f192ac48ddc5c Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Wed, 7 Sep 2011 21:10:42 +0000 Subject: [PATCH] Create Thumb2 versions of STC/LDC, and reenable the relevant tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb2.td | 104 ++++++++++++++++++++++++ lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 28 +++++++ test/MC/Disassembler/ARM/thumb-tests.txt | 7 +- 3 files changed, 134 insertions(+), 5 deletions(-) diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 91105214267..71bea1f507c 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3294,6 +3294,110 @@ def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp), [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), imm:$cp))]>, Requires<[IsThumb2]>; +//===----------------------------------------------------------------------===// +// Coprocessor load/store -- for disassembly only +// +class T2CI + : T2I { + let Inst{27-25} = 0b110; +} + +multiclass T2LdStCop op31_28, bit load, string opc> { + def _OFFSET : T2CI<(outs), + (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), + opc, "\tp$cop, cr$CRd, $addr"> { + let Inst{31-28} = op31_28; + let Inst{24} = 1; // P = 1 + let Inst{21} = 0; // W = 0 + let Inst{22} = 0; // D = 0 + let Inst{20} = load; + let DecoderMethod = "DecodeCopMemInstruction"; + } + + def _PRE : T2CI<(outs), + (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), + opc, "\tp$cop, cr$CRd, $addr!"> { + let Inst{31-28} = op31_28; + let Inst{24} = 1; // P = 1 + let Inst{21} = 1; // W = 1 + let Inst{22} = 0; // D = 0 + let Inst{20} = load; + let DecoderMethod = "DecodeCopMemInstruction"; + } + + def _POST : T2CI<(outs), + (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), + opc, "\tp$cop, cr$CRd, $addr"> { + let Inst{31-28} = op31_28; + let Inst{24} = 0; // P = 0 + let Inst{21} = 1; // W = 1 + let Inst{22} = 0; // D = 0 + let Inst{20} = load; + let DecoderMethod = "DecodeCopMemInstruction"; + } + + def _OPTION : T2CI<(outs), + (ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option), + opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> { + let Inst{31-28} = op31_28; + let Inst{24} = 0; // P = 0 + let Inst{23} = 1; // U = 1 + let Inst{21} = 0; // W = 0 + let Inst{22} = 0; // D = 0 + let Inst{20} = load; + let DecoderMethod = "DecodeCopMemInstruction"; + } + + def L_OFFSET : T2CI<(outs), + (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), + !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> { + let Inst{31-28} = op31_28; + let Inst{24} = 1; // P = 1 + let Inst{21} = 0; // W = 0 + let Inst{22} = 1; // D = 1 + let Inst{20} = load; + let DecoderMethod = "DecodeCopMemInstruction"; + } + + def L_PRE : T2CI<(outs), + (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), + !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> { + let Inst{31-28} = op31_28; + let Inst{24} = 1; // P = 1 + let Inst{21} = 1; // W = 1 + let Inst{22} = 1; // D = 1 + let Inst{20} = load; + let DecoderMethod = "DecodeCopMemInstruction"; + } + + def L_POST : T2CI<(outs), + (ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr, + postidx_imm8s4:$offset), + !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr, $offset"> { + let Inst{31-28} = op31_28; + let Inst{24} = 0; // P = 0 + let Inst{21} = 1; // W = 1 + let Inst{22} = 1; // D = 1 + let Inst{20} = load; + let DecoderMethod = "DecodeCopMemInstruction"; + } + + def L_OPTION : T2CI<(outs), + (ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option), + !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> { + let Inst{31-28} = op31_28; + let Inst{24} = 0; // P = 0 + let Inst{23} = 1; // U = 1 + let Inst{21} = 0; // W = 0 + let Inst{22} = 1; // D = 1 + let Inst{20} = load; + let DecoderMethod = "DecodeCopMemInstruction"; + } +} + +defm t2LDC : T2LdStCop<0b1111, 1, "ldc">; +defm t2STC : T2LdStCop<0b1111, 0, "stc">; + //===----------------------------------------------------------------------===// // Move between special register and ARM core register -- for disassembly only diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index fa9eed4b47b..13e410c139e 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -997,6 +997,22 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STCL_PRE: case ARM::STCL_POST: case ARM::STCL_OPTION: + case ARM::t2LDC_OFFSET: + case ARM::t2LDC_PRE: + case ARM::t2LDC_POST: + case ARM::t2LDC_OPTION: + case ARM::t2LDCL_OFFSET: + case ARM::t2LDCL_PRE: + case ARM::t2LDCL_POST: + case ARM::t2LDCL_OPTION: + case ARM::t2STC_OFFSET: + case ARM::t2STC_PRE: + case ARM::t2STC_POST: + case ARM::t2STC_OPTION: + case ARM::t2STCL_OFFSET: + case ARM::t2STCL_PRE: + case ARM::t2STCL_POST: + case ARM::t2STCL_OPTION: if (coproc == 0xA || coproc == 0xB) return MCDisassembler::Fail; break; @@ -1021,6 +1037,12 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STCL_POST: case ARM::LDC2L_POST: case ARM::STC2L_POST: + case ARM::t2LDC_OPTION: + case ARM::t2LDCL_OPTION: + case ARM::t2STC_OPTION: + case ARM::t2STCL_OPTION: + case ARM::t2LDCL_POST: + case ARM::t2STCL_POST: break; default: Inst.addOperand(MCOperand::CreateReg(0)); @@ -1040,6 +1062,8 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, switch (Inst.getOpcode()) { case ARM::LDCL_POST: case ARM::STCL_POST: + case ARM::t2LDCL_POST: + case ARM::t2STCL_POST: case ARM::LDC2L_POST: case ARM::STC2L_POST: imm |= U << 8; @@ -1051,6 +1075,10 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STCL_OPTION: case ARM::STC2_OPTION: case ARM::STC2L_OPTION: + case ARM::t2LDC_OPTION: + case ARM::t2LDCL_OPTION: + case ARM::t2STC_OPTION: + case ARM::t2STCL_OPTION: Inst.addOperand(MCOperand::CreateImm(imm)); break; default: diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index f76ea12bebb..85e999eee38 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -218,11 +218,8 @@ # CHECK: pld [r5, #30] 0x95 0xf8 0x1e 0xf0 -# Test disabled as it was originally checking for -# the ARM encoding of stc2, and thumb2 stc2 is -# not implemented yet. -# CHECK-: stc2 p12, cr15, [r9], {137} -#0x89 0xfc 0x89 0xfc +# CHECK: stc p12, cr15, [r9], {137} +0x89 0xfc 0x89 0xfc # CHECK: vmov r1, r0, d11 0x50 0xec 0x1b 0x1b -- 2.11.0