From 8b6100048eb63001b251b974ce587f0b5202f448 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 10 Apr 2017 16:58:07 +0000 Subject: [PATCH] [X86][MMX] Add fast-isel support for MMX non-temporal writes Differential Revision: https://reviews.llvm.org/D31754 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299852 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86FastISel.cpp | 4 ++++ test/CodeGen/X86/fast-isel-nontemporal.ll | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index f225696afe2..e82f43c1e0e 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -528,6 +528,7 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, X86AddressMode &AM, MachineMemOperand *MMO, bool Aligned) { + bool HasSSE1 = Subtarget->hasSSE1(); bool HasSSE2 = Subtarget->hasSSE2(); bool HasSSE4A = Subtarget->hasSSE4A(); bool HasAVX = Subtarget->hasAVX(); @@ -588,6 +589,9 @@ bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, } else Opc = X86::ST_Fp64m; break; + case MVT::x86mmx: + Opc = (IsNonTemporal && HasSSE1) ? X86::MMX_MOVNTQmr : X86::MMX_MOVQ64mr; + break; case MVT::v4f32: if (Aligned) { if (IsNonTemporal) diff --git a/test/CodeGen/X86/fast-isel-nontemporal.ll b/test/CodeGen/X86/fast-isel-nontemporal.ll index e7c3d930e46..4140721bd5f 100644 --- a/test/CodeGen/X86/fast-isel-nontemporal.ll +++ b/test/CodeGen/X86/fast-isel-nontemporal.ll @@ -100,7 +100,7 @@ define void @test_mmx(x86_mmx* nocapture %a0, x86_mmx* nocapture %a1) { ; ALL: # BB#0: # %entry ; ALL-NEXT: movq (%rdi), %mm0 ; ALL-NEXT: psrlq $3, %mm0 -; ALL-NEXT: movq %mm0, (%rsi) +; ALL-NEXT: movntq %mm0, (%rsi) ; ALL-NEXT: retq entry: %0 = load x86_mmx, x86_mmx* %a0 -- 2.11.0