From 8b94db17a43a9d847fb088ac49bafde15ba61a6d Mon Sep 17 00:00:00 2001
From: Brendon Cahoon <bcahoon@codeaurora.org>
Date: Wed, 22 Apr 2015 15:06:40 +0000
Subject: [PATCH] Fix a type mismatch assert in SCEV division

An assert was triggered when attempting to create a new SCEV
with operands of different types in the visitAddRecExpr. In this
test case, the operand types of the numerator and denominator
are different. The SCEV division code should generate a
conservative answer when this happens.

Differential Revision: http://reviews.llvm.org/D9021


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235511 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Analysis/ScalarEvolution.cpp               |  8 +++++++
 test/Analysis/Delinearization/type_mismatch.ll | 29 ++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)
 create mode 100644 test/Analysis/Delinearization/type_mismatch.ll

diff --git a/lib/Analysis/ScalarEvolution.cpp b/lib/Analysis/ScalarEvolution.cpp
index d88b0268651..9d99b8f77c9 100644
--- a/lib/Analysis/ScalarEvolution.cpp
+++ b/lib/Analysis/ScalarEvolution.cpp
@@ -795,6 +795,14 @@ public:
     assert(Numerator->isAffine() && "Numerator should be affine");
     divide(SE, Numerator->getStart(), Denominator, &StartQ, &StartR);
     divide(SE, Numerator->getStepRecurrence(SE), Denominator, &StepQ, &StepR);
+    // Bail out if the types do not match.
+    Type *Ty = Denominator->getType();
+    if (Ty != StartQ->getType() || Ty != StartR->getType() ||
+        Ty != StepQ->getType() || Ty != StepR->getType()) {
+      Quotient = Zero;
+      Remainder = Numerator;
+      return;
+    }
     Quotient = SE.getAddRecExpr(StartQ, StepQ, Numerator->getLoop(),
                                 Numerator->getNoWrapFlags());
     Remainder = SE.getAddRecExpr(StartR, StepR, Numerator->getLoop(),
diff --git a/test/Analysis/Delinearization/type_mismatch.ll b/test/Analysis/Delinearization/type_mismatch.ll
new file mode 100644
index 00000000000..0aa9a96cb1f
--- /dev/null
+++ b/test/Analysis/Delinearization/type_mismatch.ll
@@ -0,0 +1,29 @@
+; RUN: opt < %s -analyze -delinearize
+; REQUIRES: asserts
+
+; Test that SCEV divide code doesn't crash when attempting to create a SCEV
+; with operands of different types. In this case, the visitAddRecExpr
+; function tries to create an AddRec where the start and step are different
+; types.
+
+target datalayout = "e-m:e-p:32:32-i64:64-a:0-v32:32-n16:32"
+
+define fastcc void @test() {
+entry:
+  %0 = load i16, i16* undef, align 2
+  %conv21 = zext i16 %0 to i32
+  br label %for.cond7.preheader
+
+for.cond7.preheader:
+  %p1.022 = phi i8* [ undef, %entry ], [ %add.ptr, %for.end ]
+  br label %for.body11
+
+for.body11:
+  %arrayidx.phi = phi i8* [ %p1.022, %for.cond7.preheader ], [ undef, %for.body11 ]
+  store i8 undef, i8* %arrayidx.phi, align 1
+  br i1 undef, label %for.body11, label %for.end
+
+for.end:
+  %add.ptr = getelementptr inbounds i8, i8* %p1.022, i32 %conv21
+  br label %for.cond7.preheader
+}
-- 
2.11.0