From 8bb77ddd946e8046805c24d2c0529184030af0b1 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 19 Mar 2018 17:58:41 +0000 Subject: [PATCH] [X86] Add the rest of the TEST with immediate instructions to the scheduler models to match their 8-bit counterpart. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327874 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86SchedBroadwell.td | 4 ++-- lib/Target/X86/X86SchedHaswell.td | 4 ++-- lib/Target/X86/X86SchedSandyBridge.td | 4 ++-- lib/Target/X86/X86SchedSkylakeClient.td | 4 ++-- lib/Target/X86/X86SchedSkylakeServer.td | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/lib/Target/X86/X86SchedBroadwell.td b/lib/Target/X86/X86SchedBroadwell.td index 856e5c65f5e..bd06a275d41 100755 --- a/lib/Target/X86/X86SchedBroadwell.td +++ b/lib/Target/X86/X86SchedBroadwell.td @@ -840,8 +840,8 @@ def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)rr")>; def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)i")>; def: InstRW<[BWWriteResGroup9], (instregex "SYSCALL")>; def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)rr")>; -def: InstRW<[BWWriteResGroup9], (instregex "TEST8i8")>; -def: InstRW<[BWWriteResGroup9], (instregex "TEST8ri")>; +def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)i")>; +def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)ri")>; def: InstRW<[BWWriteResGroup9], (instregex "XCHG(16|32|64)rr")>; def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)ri")>; def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)rr")>; diff --git a/lib/Target/X86/X86SchedHaswell.td b/lib/Target/X86/X86SchedHaswell.td index e2559a443ea..cac3a3b8368 100644 --- a/lib/Target/X86/X86SchedHaswell.td +++ b/lib/Target/X86/X86SchedHaswell.td @@ -1256,8 +1256,8 @@ def: InstRW<[HWWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>; def: InstRW<[HWWriteResGroup10], (instregex "SUB(8|16|32|64)i")>; def: InstRW<[HWWriteResGroup10], (instregex "SYSCALL")>; def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>; -def: InstRW<[HWWriteResGroup10], (instregex "TEST8i8")>; -def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>; +def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)i")>; +def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)ri")>; def: InstRW<[HWWriteResGroup10], (instregex "XCHG(16|32|64)rr")>; def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>; def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>; diff --git a/lib/Target/X86/X86SchedSandyBridge.td b/lib/Target/X86/X86SchedSandyBridge.td index a8372e76023..e8b259cc42e 100644 --- a/lib/Target/X86/X86SchedSandyBridge.td +++ b/lib/Target/X86/X86SchedSandyBridge.td @@ -649,8 +649,8 @@ def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)ri")>; def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)rr")>; def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)i")>; def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "TEST8i8")>; -def: InstRW<[SBWriteResGroup6], (instregex "TEST8ri")>; +def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)i")>; +def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)ri")>; def: InstRW<[SBWriteResGroup6], (instregex "VMOVPQI2QIrr")>; def: InstRW<[SBWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>; def: InstRW<[SBWriteResGroup6], (instregex "VPANDNrr")>; diff --git a/lib/Target/X86/X86SchedSkylakeClient.td b/lib/Target/X86/X86SchedSkylakeClient.td index 1891f13cda7..01b87bc1230 100644 --- a/lib/Target/X86/X86SchedSkylakeClient.td +++ b/lib/Target/X86/X86SchedSkylakeClient.td @@ -846,8 +846,8 @@ def: InstRW<[SKLWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>; def: InstRW<[SKLWriteResGroup10], (instregex "SUB(8|16|32|64)i")>; def: InstRW<[SKLWriteResGroup10], (instregex "SYSCALL")>; def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>; -def: InstRW<[SKLWriteResGroup10], (instregex "TEST8i8")>; -def: InstRW<[SKLWriteResGroup10], (instregex "TEST8ri")>; +def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)i")>; +def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)ri")>; def: InstRW<[SKLWriteResGroup10], (instregex "XCHG(16|32|64)rr")>; def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>; def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>; diff --git a/lib/Target/X86/X86SchedSkylakeServer.td b/lib/Target/X86/X86SchedSkylakeServer.td index 42de233cdbd..72fff2d0f1d 100755 --- a/lib/Target/X86/X86SchedSkylakeServer.td +++ b/lib/Target/X86/X86SchedSkylakeServer.td @@ -1276,8 +1276,8 @@ def: InstRW<[SKXWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>; def: InstRW<[SKXWriteResGroup10], (instregex "SUB(8|16|32|64)i")>; def: InstRW<[SKXWriteResGroup10], (instregex "SYSCALL")>; def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>; -def: InstRW<[SKXWriteResGroup10], (instregex "TEST8i8")>; -def: InstRW<[SKXWriteResGroup10], (instregex "TEST8ri")>; +def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)i")>; +def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)ri")>; def: InstRW<[SKXWriteResGroup10], (instregex "XCHG(16|32|64)rr")>; def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>; def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>; -- 2.11.0