From 8d68aa6576dab752fe4025bbc7454f8d45043999 Mon Sep 17 00:00:00 2001 From: uros Date: Tue, 13 Apr 2010 10:27:03 +0000 Subject: [PATCH] * config/i386/i386.md (extendsidi2 splitter): Also check for DX_REG when generating cltd insn. (*ashl3_1): Remove special handling for register operand 2. (*ashlsi3_1_zext): Ditto. (*ashlhi3_1): Ditto. (*ashlhi3_1_lea): Ditto. (*ashlqi3_1): Ditto. (*ashlqi3_1_lea): Ditto. (*3_1): Ditto. (*si3_1_zext): Ditto. (*qi3_1_slp): Ditto. (*3_1): Ditto. (*si3_1_zext): Ditto. (*qi3_1_slp): Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158261 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 21 +++++++++-- gcc/config/i386/i386.md | 94 +++++++++++++++---------------------------------- 2 files changed, 47 insertions(+), 68 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 24b22881e99..c121b8af07f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,21 @@ +2010-04-13 Uros Bizjak + + * config/i386/i386.md (extendsidi2 splitter): Also check for DX_REG + when generating cltd insn. + + (*ashl3_1): Remove special handling for register operand 2. + (*ashlsi3_1_zext): Ditto. + (*ashlhi3_1): Ditto. + (*ashlhi3_1_lea): Ditto. + (*ashlqi3_1): Ditto. + (*ashlqi3_1_lea): Ditto. + (*3_1): Ditto. + (*si3_1_zext): Ditto. + (*qi3_1_slp): Ditto. + (*3_1): Ditto. + (*si3_1_zext): Ditto. + (*qi3_1_slp): Ditto. + 2010-04-13 Richard Guenther * tree-ssa-structalias.c (callused_id): Remove. @@ -126,8 +144,7 @@ plugin name. (default_plugin_dir_name): Added new function. - * common.opt (iplugindir): New option to set the plugin - directory. + * common.opt (iplugindir): New option to set the plugin directory. 2010-04-12 Uros Bizjak diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 0b0a4f4ff36..c5ac56befb5 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -9770,14 +9770,9 @@ gcc_assert (rtx_equal_p (operands[0], operands[1])); return "add{}\t%0, %0"; - case TYPE_LEA: - return "#"; - default: - if (REG_P (operands[2])) - return "sal{}\t{%b2, %0|%0, %b2}"; - else if (operands[2] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) return "sal{}\t%0"; else return "sal{}\t{%2, %0|%0, %2}"; @@ -9821,14 +9816,9 @@ gcc_assert (operands[2] == const1_rtx); return "add{l}\t%k0, %k0"; - case TYPE_LEA: - return "#"; - default: - if (REG_P (operands[2])) - return "sal{l}\t{%b2, %k0|%k0, %b2}"; - else if (operands[2] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) return "sal{l}\t%k0"; else return "sal{l}\t{%2, %k0|%k0, %2}"; @@ -9869,10 +9859,8 @@ return "add{w}\t%0, %0"; default: - if (REG_P (operands[2])) - return "sal{w}\t{%b2, %0|%0, %b2}"; - else if (operands[2] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) return "sal{w}\t%0"; else return "sal{w}\t{%2, %0|%0, %2}"; @@ -9909,6 +9897,7 @@ { case TYPE_LEA: return "#"; + case TYPE_ALU: gcc_assert (operands[2] == const1_rtx); return "add{w}\t%0, %0"; @@ -9918,10 +9907,8 @@ return "add{w}\t%0, %0"; default: - if (REG_P (operands[2])) - return "sal{w}\t{%b2, %0|%0, %b2}"; - else if (operands[2] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) return "sal{w}\t%0"; else return "sal{w}\t{%2, %0|%0, %2}"; @@ -9966,18 +9953,11 @@ return "add{b}\t%0, %0"; default: - if (REG_P (operands[2])) - { - if (get_attr_mode (insn) == MODE_SI) - return "sal{l}\t{%b2, %k0|%k0, %b2}"; - else - return "sal{b}\t{%b2, %0|%0, %b2}"; - } - else if (operands[2] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) { if (get_attr_mode (insn) == MODE_SI) - return "sal{l}\t%0"; + return "sal{l}\t%k0"; else return "sal{b}\t%0"; } @@ -10022,6 +10002,7 @@ { case TYPE_LEA: return "#"; + case TYPE_ALU: gcc_assert (operands[2] == const1_rtx); if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1])) @@ -10030,18 +10011,11 @@ return "add{b}\t%0, %0"; default: - if (REG_P (operands[2])) - { - if (get_attr_mode (insn) == MODE_SI) - return "sal{l}\t{%b2, %k0|%k0, %b2}"; - else - return "sal{b}\t{%b2, %0|%0, %b2}"; - } - else if (operands[2] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) { if (get_attr_mode (insn) == MODE_SI) - return "sal{l}\t%0"; + return "sal{l}\t%k0"; else return "sal{b}\t%0"; } @@ -10454,10 +10428,8 @@ (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands)" { - if (REG_P (operands[2])) - return "{}\t{%b2, %0|%0, %b2}"; - else if (operands[2] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) return "{}\t%0"; else return "{}\t{%2, %0|%0, %2}"; @@ -10480,10 +10452,8 @@ (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (, SImode, operands)" { - if (REG_P (operands[2])) - return "{l}\t{%b2, %k0|%k0, %b2}"; - else if (operands[2] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) return "{l}\t%k0"; else return "{l}\t{%2, %k0|%k0, %2}"; @@ -10508,10 +10478,8 @@ || (operands[1] == const1_rtx && TARGET_SHIFT1))" { - if (REG_P (operands[1])) - return "{b}\t{%b1, %0|%0, %b1}"; - else if (operands[1] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + if (operands[1] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) return "{b}\t%0"; else return "{b}\t{%1, %0|%0, %1}"; @@ -10731,10 +10699,8 @@ (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands)" { - if (REG_P (operands[2])) - return "{}\t{%b2, %0|%0, %b2}"; - else if (operands[2] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) return "{}\t%0"; else return "{}\t{%2, %0|%0, %2}"; @@ -10757,10 +10723,8 @@ (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (, SImode, operands)" { - if (REG_P (operands[2])) - return "{l}\t{%b2, %k0|%k0, %b2}"; - else if (operands[2] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) return "{l}\t%k0"; else return "{l}\t{%2, %k0|%k0, %2}"; @@ -10785,10 +10749,8 @@ || (operands[1] == const1_rtx && TARGET_SHIFT1))" { - if (REG_P (operands[1])) - return "{b}\t{%b1, %0|%0, %b1}"; - else if (operands[1] == const1_rtx - && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + if (operands[1] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) return "{b}\t%0"; else return "{b}\t{%1, %0|%0, %1}"; -- 2.11.0