From 8da41e8bffded2b3f59fe9ef5b4bd0b9b4c71162 Mon Sep 17 00:00:00 2001 From: astoria-d Date: Sun, 27 Oct 2013 12:05:08 +0900 Subject: [PATCH] ppu address reg set timing updated --- de1_nes/de1_nes.vhd | 6 +++++ de1_nes/ppu/ppu.vhd | 28 ++++++++++++---------- .../modelsim/de1_nes_run_msim_gate_vhdl.do | 6 +++++ .../modelsim/de1_nes_run_msim_rtl_vhdl.do | 21 +++++++++++++--- de1_nes/testbench_motones_sim.vhd | 7 +++++- 5 files changed, 51 insertions(+), 17 deletions(-) diff --git a/de1_nes/de1_nes.vhd b/de1_nes/de1_nes.vhd index 7689594..777d982 100644 --- a/de1_nes/de1_nes.vhd +++ b/de1_nes/de1_nes.vhd @@ -40,6 +40,8 @@ entity de1_nes is -- signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); -- signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_ppu_addr_we_n : out std_logic; + signal dbg_ppu_clk_cnt : out std_logic_vector(1 downto 0); @@ -143,6 +145,8 @@ architecture rtl of de1_nes is signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0); signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_ppu_addr_we_n : out std_logic; + signal dbg_ppu_clk_cnt : out std_logic_vector(1 downto 0); clk : in std_logic; mem_clk : in std_logic; @@ -305,6 +309,8 @@ begin dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status, dbg_ppu_addr, dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y, dbg_disp_nt, dbg_disp_attr, dbg_disp_ptn_h, dbg_disp_ptn_l , + dbg_ppu_addr_we_n , + dbg_ppu_clk_cnt , ppu_clk, mem_clk, ppu_ce_n, rst_n, r_nw, addr(2 downto 0), d_io, nmi_n, rd_n, wr_n, ale, vram_ad, vram_a, diff --git a/de1_nes/ppu/ppu.vhd b/de1_nes/ppu/ppu.vhd index 972af76..20ccec0 100644 --- a/de1_nes/ppu/ppu.vhd +++ b/de1_nes/ppu/ppu.vhd @@ -10,7 +10,9 @@ entity ppu is signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0); signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); - + signal dbg_ppu_addr_we_n : out std_logic; + signal dbg_ppu_clk_cnt : out std_logic_vector(1 downto 0); + clk : in std_logic; mem_clk : in std_logic; @@ -193,6 +195,8 @@ begin dbg_ppu_data <= ppu_data; dbg_ppu_scrl_x <= ppu_scroll_x; dbg_ppu_scrl_y <= ppu_scroll_y; + dbg_ppu_addr_we_n <= ppu_addr_we_n; + dbg_ppu_clk_cnt <= ppu_clk_cnt; @@ -327,14 +331,11 @@ begin end if; if(cpu_addr = PPUADDR) then - ppu_addr_we_n <= '0'; if (ppu_addr_cnt(0) = '0') then ppu_addr_in <= cpu_d(5 downto 0) & ppu_addr(7 downto 0); else ppu_addr_in <= ppu_addr(13 downto 8) & cpu_d; end if; - else - ppu_addr_we_n <= '1'; end if; if (cpu_addr = PPUDATA and r_nw = '1') then @@ -350,20 +351,21 @@ begin ppu_scroll_x_we_n <= '1'; ppu_scroll_y_we_n <= '1'; ppu_scroll_cnt_ce_n <= '1'; - ppu_addr_we_n <= '1'; read_status <= '0'; read_data_n <= '1'; end if; --if (rst_n = '1' and ce_n = '0') end process; + ppu_clk_cnt_res_n <= not ce_n; + --cpu and ppu clock timing adjustment... clk_cnt_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d, clk, oam_plt_data, vram_ad, ppu_stat_out) begin if (rst_n = '0') then ppu_latch_rst_n <= '0'; - ppu_clk_cnt_res_n <= '0'; + ppu_addr_we_n <= '1'; rd_n <= 'Z'; wr_n <= 'Z'; ale <= 'Z'; @@ -380,12 +382,6 @@ begin --start counter. if (clk'event and clk = '0') then - if (ppu_clk_cnt = "10") then - ppu_clk_cnt_res_n <= '0'; - elsif (ppu_clk_cnt = "00") then - ppu_clk_cnt_res_n <= '1'; - end if; - if (read_status = '1') then --reading status resets ppu_addr/scroll cnt. ppu_latch_rst_n <= '0'; @@ -414,6 +410,12 @@ begin end if; --if (cpu_addr = OAMDATA and ppu_clk_cnt = "00") then --vram address access. + if(cpu_addr = PPUADDR and ppu_clk_cnt = "00") then + ppu_addr_we_n <= '0'; + else + ppu_addr_we_n <= '1'; + end if; + if (cpu_addr = PPUADDR and ppu_clk_cnt = "00") then ppu_addr_cnt_ce_n <= '0'; if (ppu_addr_cnt(0) = '0') then @@ -496,9 +498,9 @@ begin end if; else + ppu_addr_we_n <= '1'; ppu_data_we_n <= '1'; plt_bus_ce_n <= '1'; - ppu_clk_cnt_res_n <= '0'; oam_bus_ce_n <= '1'; oam_addr_ce_n <= '1'; ppu_addr_cnt_ce_n <= '1'; diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do index 3a58e3c..548ca21 100644 --- a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do +++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do @@ -48,6 +48,11 @@ add wave -divider ppu add wave sim:/testbench_motones_sim/sim_board/dbg_ppu_ce_n add wave sim:/testbench_motones_sim/sim_board/dbg_ppu_clk + +add wave sim:/testbench_motones_sim/dbg_ppu_addr_we_n +add wave -radix hex sim:/testbench_motones_sim/dbg_ppu_clk_cnt + + add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status @@ -85,6 +90,7 @@ view structure view signals #run -all run 10 us +run 50 us #wave zoom range 3339700 ps 5138320 ps wave zoom full diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do index 0f9c808..2d7ef30 100644 --- a/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do +++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do @@ -36,19 +36,34 @@ add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/instruction add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/int_d_bus add wave -divider regs add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/acc/q -add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/sp/q add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_register/status_val +add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/sp/q add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/x/q add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/y/q -add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_reg +##add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_reg + +add wave -divider ppu + +add wave sim:/testbench_motones_sim/sim_board/dbg_ppu_ce_n +add wave sim:/testbench_motones_sim/sim_board/dbg_ppu_clk + +add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt +add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl +add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask +add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status +add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_addr +add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_data +add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x +add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y ###add wave sim:/testbench_motones_sim/sim_board/cpu_inst/* view structure view signals -run 100 us +#run 100 us +run 60 us wave zoom full diff --git a/de1_nes/testbench_motones_sim.vhd b/de1_nes/testbench_motones_sim.vhd index 1278c7c..b6ec07f 100644 --- a/de1_nes/testbench_motones_sim.vhd +++ b/de1_nes/testbench_motones_sim.vhd @@ -37,6 +37,8 @@ architecture stimulus of testbench_motones_sim is signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0); -- signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); -- signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_ppu_addr_we_n : out std_logic; + signal dbg_ppu_clk_cnt : out std_logic_vector(1 downto 0); --NES instance @@ -111,6 +113,8 @@ architecture stimulus of testbench_motones_sim is signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : std_logic_vector (7 downto 0); signal dbg_disp_nt, dbg_disp_attr : std_logic_vector (7 downto 0); signal dbg_disp_ptn_h, dbg_disp_ptn_l : std_logic_vector (15 downto 0); + signal dbg_ppu_addr_we_n : std_logic; + signal dbg_ppu_clk_cnt : std_logic_vector(1 downto 0); begin @@ -142,7 +146,8 @@ dbg_ppu_addr , dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y, --dbg_disp_nt, dbg_disp_attr , --dbg_disp_ptn_h, dbg_disp_ptn_l , - +dbg_ppu_addr_we_n, +dbg_ppu_clk_cnt , base_clk, reset_input, joypad1, joypad2, -- 2.11.0