From 8ebdc2bdbbae5dd014bce8d438f0eca02bad9ff9 Mon Sep 17 00:00:00 2001 From: Andreas Gampe Date: Wed, 14 Jan 2015 12:09:25 -0800 Subject: [PATCH] ART: Fix indentation in Mips backend Fix the indentation to be standard. Change-Id: I39a16716be3429dfef6df0a585e24423b46363a2 --- compiler/dex/quick/mips/assemble_mips.cc | 2 +- compiler/dex/quick/mips/codegen_mips.h | 3 +- compiler/dex/quick/mips/int_mips.cc | 14 +-- compiler/dex/quick/mips/target_mips.cc | 142 +++++++++++++++---------------- compiler/dex/quick/mips/utility_mips.cc | 20 ++--- 5 files changed, 91 insertions(+), 90 deletions(-) diff --git a/compiler/dex/quick/mips/assemble_mips.cc b/compiler/dex/quick/mips/assemble_mips.cc index c48833b27..4265ae119 100644 --- a/compiler/dex/quick/mips/assemble_mips.cc +++ b/compiler/dex/quick/mips/assemble_mips.cc @@ -482,7 +482,7 @@ void MipsMir2Lir::ConvertShortToLongBranch(LIR* lir) { if (!unconditional) { hop_target = RawLIR(dalvik_offset, kPseudoTargetLabel); LIR* hop_branch = RawLIR(dalvik_offset, opcode, lir->operands[0], - lir->operands[1], 0, 0, 0, hop_target); + lir->operands[1], 0, 0, 0, hop_target); InsertLIRBefore(lir, hop_branch); } LIR* curr_pc = RawLIR(dalvik_offset, kMipsCurrPC); diff --git a/compiler/dex/quick/mips/codegen_mips.h b/compiler/dex/quick/mips/codegen_mips.h index 8f976df09..9c3ce7bf5 100644 --- a/compiler/dex/quick/mips/codegen_mips.h +++ b/compiler/dex/quick/mips/codegen_mips.h @@ -216,7 +216,8 @@ class MipsMir2Lir FINAL : public Mir2Lir { void ConvertShortToLongBranch(LIR* lir); RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_div, int flags) OVERRIDE; - RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) OVERRIDE; + RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) + OVERRIDE; }; } // namespace art diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc index 0778c3bad..aabef60c3 100644 --- a/compiler/dex/quick/mips/int_mips.cc +++ b/compiler/dex/quick/mips/int_mips.cc @@ -172,7 +172,7 @@ LIR* MipsMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { if (r_dest.IsFloat() || r_src.IsFloat()) return OpFpRegCopy(r_dest, r_src); LIR* res = RawLIR(current_dalvik_offset_, kMipsMove, - r_dest.GetReg(), r_src.GetReg()); + r_dest.GetReg(), r_src.GetReg()); if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { res->flags.is_nop = true; } @@ -194,7 +194,7 @@ void MipsMir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { if (src_fp) { OpRegCopy(r_dest, r_src); } else { - /* note the operands are swapped for the mtc1 instr */ + /* note the operands are swapped for the mtc1 instr */ NewLIR2(kMipsMtc1, r_src.GetLowReg(), r_dest.GetLowReg()); NewLIR2(kMipsMtc1, r_src.GetHighReg(), r_dest.GetHighReg()); } @@ -240,7 +240,7 @@ void MipsMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { } RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2, - bool is_div) { + bool is_div) { NewLIR2(kMipsDiv, reg1.GetReg(), reg2.GetReg()); RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); if (is_div) { @@ -252,7 +252,7 @@ RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStor } RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, - bool is_div) { + bool is_div) { RegStorage t_reg = AllocTemp(); NewLIR3(kMipsAddiu, t_reg.GetReg(), rZERO, lit); NewLIR2(kMipsDiv, reg1.GetReg(), t_reg.GetReg()); @@ -501,7 +501,7 @@ void MipsMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { * Generate array load */ void MipsMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, - RegLocation rl_index, RegLocation rl_dest, int scale) { + RegLocation rl_index, RegLocation rl_dest, int scale) { RegisterClass reg_class = RegClassBySize(size); int len_offset = mirror::Array::LengthOffset().Int32Value(); int data_offset; @@ -570,7 +570,7 @@ void MipsMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, * */ void MipsMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, - RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { + RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { RegisterClass reg_class = RegClassBySize(size); int len_offset = mirror::Array::LengthOffset().Int32Value(); int data_offset; @@ -632,7 +632,7 @@ void MipsMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, } else { rl_src = LoadValue(rl_src, reg_class); if (needs_range_check) { - GenArrayBoundsCheck(rl_index.reg, reg_len); + GenArrayBoundsCheck(rl_index.reg, reg_len); FreeTemp(reg_len); } StoreBaseIndexed(reg_ptr, rl_index.reg, rl_src.reg, scale, size); diff --git a/compiler/dex/quick/mips/target_mips.cc b/compiler/dex/quick/mips/target_mips.cc index c22ba04e0..c819903b7 100644 --- a/compiler/dex/quick/mips/target_mips.cc +++ b/compiler/dex/quick/mips/target_mips.cc @@ -89,9 +89,9 @@ RegLocation MipsMir2Lir::LocCReturnDouble() { // Convert k64BitSolo into k64BitPair RegStorage MipsMir2Lir::Solo64ToPair64(RegStorage reg) { - DCHECK(reg.IsDouble()); - int reg_num = (reg.GetRegNum() & ~1) | RegStorage::kFloatingPoint; - return RegStorage(RegStorage::k64BitPair, reg_num, reg_num + 1); + DCHECK(reg.IsDouble()); + int reg_num = (reg.GetRegNum() & ~1) | RegStorage::kFloatingPoint; + return RegStorage(RegStorage::k64BitPair, reg_num, reg_num + 1); } // Return a target-dependent special register. @@ -223,78 +223,78 @@ std::string MipsMir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned cha if (nc == '!') { strcpy(tbuf, "!"); } else { - DCHECK_LT(fmt, fmt_end); - DCHECK_LT(static_cast(nc-'0'), 4u); - operand = lir->operands[nc-'0']; - switch (*fmt++) { - case 'b': - strcpy(tbuf, "0000"); - for (i = 3; i >= 0; i--) { - tbuf[i] += operand & 1; - operand >>= 1; - } - break; - case 's': - snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand)); - break; - case 'S': - DCHECK_EQ(RegStorage::RegNum(operand) & 1, 0); - snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand)); - break; - case 'h': - snprintf(tbuf, arraysize(tbuf), "%04x", operand); - break; - case 'M': - case 'd': - snprintf(tbuf, arraysize(tbuf), "%d", operand); - break; - case 'D': - snprintf(tbuf, arraysize(tbuf), "%d", operand+1); - break; - case 'E': - snprintf(tbuf, arraysize(tbuf), "%d", operand*4); - break; - case 'F': - snprintf(tbuf, arraysize(tbuf), "%d", operand*2); - break; - case 't': - snprintf(tbuf, arraysize(tbuf), "0x%08" PRIxPTR " (L%p)", - reinterpret_cast(base_addr) + lir->offset + 4 + (operand << 1), - lir->target); - break; - case 'T': - snprintf(tbuf, arraysize(tbuf), "0x%08x", operand << 2); - break; - case 'u': { - int offset_1 = lir->operands[0]; - int offset_2 = NEXT_LIR(lir)->operands[0]; - uintptr_t target = - (((reinterpret_cast(base_addr) + lir->offset + 4) & ~3) + - (offset_1 << 21 >> 9) + (offset_2 << 1)) & 0xfffffffc; - snprintf(tbuf, arraysize(tbuf), "%p", reinterpret_cast(target)); - break; + DCHECK_LT(fmt, fmt_end); + DCHECK_LT(static_cast(nc-'0'), 4u); + operand = lir->operands[nc-'0']; + switch (*fmt++) { + case 'b': + strcpy(tbuf, "0000"); + for (i = 3; i >= 0; i--) { + tbuf[i] += operand & 1; + operand >>= 1; + } + break; + case 's': + snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand)); + break; + case 'S': + DCHECK_EQ(RegStorage::RegNum(operand) & 1, 0); + snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand)); + break; + case 'h': + snprintf(tbuf, arraysize(tbuf), "%04x", operand); + break; + case 'M': + case 'd': + snprintf(tbuf, arraysize(tbuf), "%d", operand); + break; + case 'D': + snprintf(tbuf, arraysize(tbuf), "%d", operand+1); + break; + case 'E': + snprintf(tbuf, arraysize(tbuf), "%d", operand*4); + break; + case 'F': + snprintf(tbuf, arraysize(tbuf), "%d", operand*2); + break; + case 't': + snprintf(tbuf, arraysize(tbuf), "0x%08" PRIxPTR " (L%p)", + reinterpret_cast(base_addr) + lir->offset + 4 + (operand << 1), + lir->target); + break; + case 'T': + snprintf(tbuf, arraysize(tbuf), "0x%08x", operand << 2); + break; + case 'u': { + int offset_1 = lir->operands[0]; + int offset_2 = NEXT_LIR(lir)->operands[0]; + uintptr_t target = + (((reinterpret_cast(base_addr) + lir->offset + 4) & ~3) + + (offset_1 << 21 >> 9) + (offset_2 << 1)) & 0xfffffffc; + snprintf(tbuf, arraysize(tbuf), "%p", reinterpret_cast(target)); + break; } - /* Nothing to print for BLX_2 */ - case 'v': - strcpy(tbuf, "see above"); - break; - case 'r': - DCHECK(operand >= 0 && operand < MIPS_REG_COUNT); - strcpy(tbuf, mips_reg_name[operand]); - break; - case 'N': - // Placeholder for delay slot handling - strcpy(tbuf, "; nop"); - break; - default: - strcpy(tbuf, "DecodeError"); - break; - } - buf += tbuf; + /* Nothing to print for BLX_2 */ + case 'v': + strcpy(tbuf, "see above"); + break; + case 'r': + DCHECK(operand >= 0 && operand < MIPS_REG_COUNT); + strcpy(tbuf, mips_reg_name[operand]); + break; + case 'N': + // Placeholder for delay slot handling + strcpy(tbuf, "; nop"); + break; + default: + strcpy(tbuf, "DecodeError"); + break; + } + buf += tbuf; } } else { - buf += *fmt++; + buf += *fmt++; } } return buf; diff --git a/compiler/dex/quick/mips/utility_mips.cc b/compiler/dex/quick/mips/utility_mips.cc index adb927069..15fc69d4a 100644 --- a/compiler/dex/quick/mips/utility_mips.cc +++ b/compiler/dex/quick/mips/utility_mips.cc @@ -228,17 +228,17 @@ LIR* MipsMir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, i } break; case kOpLsl: - DCHECK(value >= 0 && value <= 31); - opcode = kMipsSll; - break; + DCHECK(value >= 0 && value <= 31); + opcode = kMipsSll; + break; case kOpLsr: - DCHECK(value >= 0 && value <= 31); - opcode = kMipsSrl; - break; + DCHECK(value >= 0 && value <= 31); + opcode = kMipsSrl; + break; case kOpAsr: - DCHECK(value >= 0 && value <= 31); - opcode = kMipsSra; - break; + DCHECK(value >= 0 && value <= 31); + opcode = kMipsSra; + break; case kOpAnd: if (IS_UIMM16((value))) { opcode = kMipsAndi; @@ -324,7 +324,7 @@ LIR* MipsMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) } return res; case kOp2Char: - return NewLIR3(kMipsAndi, r_dest_src1.GetReg(), r_src2.GetReg(), 0xFFFF); + return NewLIR3(kMipsAndi, r_dest_src1.GetReg(), r_src2.GetReg(), 0xFFFF); default: LOG(FATAL) << "Bad case in OpRegReg"; UNREACHABLE(); -- 2.11.0