From 8ecfdbf04eed6c3c7c5bb7e5960a7b115fe60833 Mon Sep 17 00:00:00 2001 From: yujiro_kaeko Date: Thu, 7 Jul 2011 21:07:20 +0900 Subject: [PATCH] Change-Id: I11928c8b3de2e1173d8e60e818367c7276c8328e --- VGADisplay/Verilog/FIFO.v | 13 + VGADisplay/Verilog/exp_ctrl.v | 112 +++++ VGADisplay/Verilog/from_ctrl.v | 13 + VGADisplay/Verilog/ram_test.v | 16 + VGADisplay/Verilog/vga_generate.v | 653 ++++++++++++++++++++++++++++ VGADisplay/Verilog/vga_top.v | 875 ++++++++++++++++++++++++++++++++++++++ VGADisplay/Verilog/vram.v | 34 ++ VGADisplay/Verilog/vram_ctrl.v | 65 +++ VGADisplay/src/exp_ctrl.nsh | 10 + VGADisplay/src/exp_ctrl.nsl | 50 ++- VGADisplay/src/vga_top.nsl | 107 ++--- VGADisplay/src/vram.nsh | 22 +- VGADisplay/src/vram.nsl | 26 ++ VGADisplay/src/vram_ctrl.nsl | 49 ++- 14 files changed, 1935 insertions(+), 110 deletions(-) create mode 100644 VGADisplay/Verilog/FIFO.v create mode 100644 VGADisplay/Verilog/exp_ctrl.v create mode 100644 VGADisplay/Verilog/from_ctrl.v create mode 100644 VGADisplay/Verilog/ram_test.v create mode 100644 VGADisplay/Verilog/vga_generate.v create mode 100644 VGADisplay/Verilog/vga_top.v create mode 100644 VGADisplay/Verilog/vram.v create mode 100644 VGADisplay/Verilog/vram_ctrl.v create mode 100644 VGADisplay/src/exp_ctrl.nsh create mode 100644 VGADisplay/src/vram.nsl diff --git a/VGADisplay/Verilog/FIFO.v b/VGADisplay/Verilog/FIFO.v new file mode 100644 index 0000000..7fa7dff --- /dev/null +++ b/VGADisplay/Verilog/FIFO.v @@ -0,0 +1,13 @@ +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:40 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER: +*/ + +module FIFO ( p_reset , m_clock ); + input p_reset, m_clock; + +endmodule +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:40 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp +*/ diff --git a/VGADisplay/Verilog/exp_ctrl.v b/VGADisplay/Verilog/exp_ctrl.v new file mode 100644 index 0000000..57feed7 --- /dev/null +++ b/VGADisplay/Verilog/exp_ctrl.v @@ -0,0 +1,112 @@ +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:02:46 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER: +*/ + +module vram_ctrl ( p_reset , m_clock , i_Wdata , i_Wadrs , i_Radrs , o_Rdata , fi_Wr_req , fi_Rd_req , fo_Rd_ack ); + input p_reset, m_clock; + input [7:0] i_Wdata; + input [13:0] i_Wadrs; + input [13:0] i_Radrs; + output [7:0] o_Rdata; + input fi_Wr_req; + input fi_Rd_req; + output fo_Rd_ack; + reg [13:0] r_Radrs_hld; + wire _u_VRAM_clk; + wire [7:0] _u_VRAM_d; + wire [13:0] _u_VRAM_ra; + wire [13:0] _u_VRAM_wa; + wire _u_VRAM_we; + wire [7:0] _u_VRAM_q; + wire _u_VRAM_p_reset; + wire _u_VRAM_m_clock; + wire _net_0; + reg _reg_1; + reg _reg_2; + wire _net_3; + wire _net_4; +vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .we(_u_VRAM_we), .wa(_u_VRAM_wa), .ra(_u_VRAM_ra), .d(_u_VRAM_d), .clk(_u_VRAM_clk)); + + assign _u_VRAM_d = i_Wdata; + assign _u_VRAM_ra = ((_net_3)?i_Radrs:14'b0)| + ((_reg_1)?r_Radrs_hld:14'b0); + assign _u_VRAM_wa = i_Wadrs; + assign _u_VRAM_we = fi_Wr_req| + ((_net_0)?1'b0:1'b0); + assign _net_0 = ~fi_Wr_req; + assign _net_3 = fi_Rd_req|_reg_2; + assign _net_4 = fi_Rd_req|_reg_1|_reg_2; + assign o_Rdata = _u_VRAM_q; + assign fo_Rd_ack = _reg_1; +always @(posedge p_reset) + begin +if (p_reset) + r_Radrs_hld <= 14'b00000000000000; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + _reg_1 <= 1'b0; +else if ((_net_4)) + _reg_1 <= _reg_2|fi_Rd_req; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + _reg_2 <= 1'b0; +else if ((_reg_2)) + _reg_2 <= 1'b0; +end +endmodule +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:02:48 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp +*/ + +module exp_ctrl ( p_reset , m_clock , i_Radrs , o_Rdata , fi_Rd_req , fo_Rd_ack , i_Wdata , i_Wadrs , fi_Wr_req ); + input p_reset, m_clock; + input [13:0] i_Radrs; + output [15:0] o_Rdata; + input fi_Rd_req; + output fo_Rd_ack; + input [7:0] i_Wdata; + input [13:0] i_Wadrs; + input fi_Wr_req; + wire [15:0] w_exp_q; + wire [7:0] _u_VRAMC_i_Wdata; + wire [13:0] _u_VRAMC_i_Wadrs; + wire [13:0] _u_VRAMC_i_Radrs; + wire [7:0] _u_VRAMC_o_Rdata; + wire _u_VRAMC_fi_Wr_req; + wire _u_VRAMC_fi_Rd_req; + wire _u_VRAMC_fo_Rd_ack; + wire _u_VRAMC_p_reset; + wire _u_VRAMC_m_clock; + reg _reg_5; + wire _net_6; + wire _net_7; +vram_ctrl u_VRAMC (.p_reset(p_reset), .m_clock(m_clock), .fo_Rd_ack(_u_VRAMC_fo_Rd_ack), .fi_Rd_req(_u_VRAMC_fi_Rd_req), .fi_Wr_req(_u_VRAMC_fi_Wr_req), .o_Rdata(_u_VRAMC_o_Rdata), .i_Radrs(_u_VRAMC_i_Radrs), .i_Wadrs(_u_VRAMC_i_Wadrs), .i_Wdata(_u_VRAMC_i_Wdata)); + + assign w_exp_q = {_u_VRAMC_o_Rdata[7],_u_VRAMC_o_Rdata[7],_u_VRAMC_o_Rdata[6],_u_VRAMC_o_Rdata[6],_u_VRAMC_o_Rdata[5],_u_VRAMC_o_Rdata[5],_u_VRAMC_o_Rdata[4],_u_VRAMC_o_Rdata[4],_u_VRAMC_o_Rdata[3],_u_VRAMC_o_Rdata[3],_u_VRAMC_o_Rdata[2],_u_VRAMC_o_Rdata[2],_u_VRAMC_o_Rdata[1],_u_VRAMC_o_Rdata[1],_u_VRAMC_o_Rdata[0],_u_VRAMC_o_Rdata[0]}; + assign _u_VRAMC_i_Wdata = i_Wdata; + assign _u_VRAMC_i_Wadrs = i_Wadrs; + assign _u_VRAMC_i_Radrs = i_Radrs; + assign _u_VRAMC_fi_Wr_req = fi_Wr_req; + assign _u_VRAMC_fi_Rd_req = _net_6; + assign _net_6 = fi_Rd_req|_reg_5; + assign _net_7 = fi_Rd_req|_reg_5; + assign o_Rdata = w_exp_q; + assign fo_Rd_ack = _u_VRAMC_fo_Rd_ack; +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + _reg_5 <= 1'b0; +else if ((_reg_5)) + _reg_5 <= 1'b0; +end +endmodule +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:02:48 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp +*/ diff --git a/VGADisplay/Verilog/from_ctrl.v b/VGADisplay/Verilog/from_ctrl.v new file mode 100644 index 0000000..1124668 --- /dev/null +++ b/VGADisplay/Verilog/from_ctrl.v @@ -0,0 +1,13 @@ +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:37 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER: +*/ + +module from_ctrl ( p_reset , m_clock ); + input p_reset, m_clock; + +endmodule +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:37 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp +*/ diff --git a/VGADisplay/Verilog/ram_test.v b/VGADisplay/Verilog/ram_test.v new file mode 100644 index 0000000..35fe833 --- /dev/null +++ b/VGADisplay/Verilog/ram_test.v @@ -0,0 +1,16 @@ +module vram ( q, wa, ra, d, we, clk ); + output [7:0] q ; + input [7:0] d ; + input [13:0] wa ; + input [13:0] ra ; + input we, clk ; + reg [13:0] read_add ; + (* remstyle = "no_rw_check" *) reg [7:0] mem[16383:0]; + always @ (posedge clk) begin + if(we) + mem[wa] <= d ; + read_add <= ra ; + end + + assign q = mem[read_add]; +endmodule diff --git a/VGADisplay/Verilog/vga_generate.v b/VGADisplay/Verilog/vga_generate.v new file mode 100644 index 0000000..1886b9c --- /dev/null +++ b/VGADisplay/Verilog/vga_generate.v @@ -0,0 +1,653 @@ +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:33 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER: +*/ + +module vga_generate ( p_reset , m_clock , pix32_data_i , v_sync_o , h_sync_o , vga_red_o , vga_green_o , vga_blue_o , h_cnt_o , ack_req_32dot , req_32dot ); + input p_reset; + input m_clock; + input [31:0] pix32_data_i; + output v_sync_o; + output h_sync_o; + output [3:0] vga_red_o; + output [3:0] vga_green_o; + output [3:0] vga_blue_o; + output [9:0] h_cnt_o; + input ack_req_32dot; + output req_32dot; + wire disp_data; + reg v_sync; + reg h_sync; + reg h_flg; + reg vdata_flg; + reg hdata_flg; + reg [9:0] h_cnt; + reg [18:0] v_cnt; + reg [4:0] bit32_cnt; + reg reg_flg; + reg reg_cnt; + reg [31:0] r1; + reg [31:0] r2; + reg data_select_flag; + wire [3:0] red; + wire [3:0] green; + wire [3:0] blue; + wire sel_disp_data; + wire _net_0; + wire _net_1; + wire _net_2; + wire _net_3; + wire _net_4; + wire _net_5; + wire _net_6; + wire _net_7; + wire _net_8; + wire _net_9; + wire _net_10; + wire _net_11; + wire _net_12; + wire _net_13; + wire _net_14; + wire _net_15; + wire _net_16; + wire _net_17; + wire _net_18; + wire _net_19; + wire _net_20; + wire _net_21; + wire _net_22; + wire _net_23; + wire _net_24; + wire _net_25; + wire _net_26; + wire _net_27; + wire _net_28; + wire _net_29; + wire _net_30; + wire _net_31; + wire _net_32; + wire _net_33; + wire _net_34; + wire _net_35; + wire _net_36; + wire _net_37; + wire _net_38; + wire _net_39; + wire _net_40; + wire _net_41; + wire _net_42; + wire _net_43; + wire _net_44; + wire _net_45; + wire _net_46; + wire _net_47; + wire _net_48; + wire _net_49; + wire _net_50; + wire _net_51; + wire _net_52; + wire _net_53; + wire _net_54; + wire _net_55; + wire _net_56; + wire _net_57; + wire _net_58; + wire _net_59; + wire _net_60; + wire _net_61; + wire _net_62; + wire _net_63; + wire _net_64; + wire _net_65; + wire _net_66; + wire _net_67; + wire _net_68; + wire _net_69; + wire _net_70; + wire _net_71; + wire _net_72; + wire _net_73; + wire _net_74; + wire _net_75; + wire _net_76; + wire _net_77; + wire _net_78; + wire _net_79; + wire _net_80; + wire _net_81; + wire _net_82; + wire _net_83; + wire _net_84; + wire _net_85; + wire _net_86; + wire _net_87; + wire _net_88; + wire _net_89; + wire _net_90; + wire _net_91; + wire _net_92; + wire _net_93; + wire _net_94; + wire _net_95; + wire _net_96; + wire _net_97; + wire _net_98; + wire _net_99; + wire _net_100; + wire _net_101; + wire _net_102; + wire _net_103; + wire _net_104; + wire _net_105; + wire _net_106; + wire _net_107; + wire _net_108; + wire _net_109; + wire _net_110; + wire _net_111; + wire _net_112; + wire _net_113; + wire _net_114; + wire _net_115; + wire _net_116; + wire _net_117; + wire _net_118; + wire _net_119; + wire _net_120; + wire _net_121; + wire _net_122; + wire _net_123; + wire _net_124; + wire _net_125; + wire _net_126; + wire _net_127; + wire _net_128; + wire _net_129; + wire _net_130; + wire _net_131; + wire _net_132; + wire _net_133; + wire _net_134; + wire _net_135; + wire _net_136; + wire _net_137; + wire _net_138; + wire _net_139; + wire _net_140; + wire _net_141; + wire _net_142; + wire _net_143; + wire _net_144; + wire _net_145; + wire _net_146; + wire _net_147; + wire _net_148; + wire _net_149; + wire _net_150; + wire _net_151; + wire _net_152; + wire _net_153; + wire _net_154; + wire _net_155; + wire _net_156; + wire _net_157; + wire _net_158; + wire _net_159; + wire _net_160; + wire _net_161; + wire _net_162; + wire _net_163; + wire _net_164; + wire _net_165; + wire _net_166; + wire _net_167; + wire _net_168; + wire _net_169; + wire _net_170; + wire _net_171; + wire _net_172; + wire _net_173; + wire _net_174; + wire _net_175; + wire _net_176; + wire _net_177; + wire _net_178; + wire _net_179; + wire _net_180; + wire _net_181; + wire _net_182; + wire _net_183; + wire _net_184; + wire _net_185; + wire _net_186; + wire _net_187; + wire _net_188; + wire _net_189; + wire _net_190; + wire _net_191; + wire _net_192; + wire _net_193; + wire _net_194; + wire _net_195; + wire _net_196; + wire _net_197; + wire _net_198; + wire _net_199; + wire _net_200; + wire _net_201; + wire _net_202; + wire _net_203; + wire _net_204; + wire _net_205; + wire _net_206; + wire _net_207; + wire _net_208; + wire _net_209; + wire _net_210; + wire _net_211; + wire _net_212; + wire _net_213; + wire _net_214; + wire _net_215; + wire _net_216; + wire _net_217; + wire _net_218; + + assign disp_data = _net_10; + assign red = 4'b0000; + assign green = 4'b0000; + assign blue = ((_net_20)?4'b0000:4'b0)| + ((_net_18)?4'b1111:4'b0); + assign sel_disp_data = ((_net_218)?r2[31]:1'b0)| + ((_net_215)?r2[30]:1'b0)| + ((_net_212)?r2[29]:1'b0)| + ((_net_209)?r2[28]:1'b0)| + ((_net_206)?r2[27]:1'b0)| + ((_net_203)?r2[26]:1'b0)| + ((_net_200)?r2[25]:1'b0)| + ((_net_197)?r2[24]:1'b0)| + ((_net_194)?r2[23]:1'b0)| + ((_net_191)?r2[22]:1'b0)| + ((_net_188)?r2[21]:1'b0)| + ((_net_185)?r2[20]:1'b0)| + ((_net_182)?r2[19]:1'b0)| + ((_net_179)?r2[18]:1'b0)| + ((_net_176)?r2[17]:1'b0)| + ((_net_173)?r2[16]:1'b0)| + ((_net_170)?r2[15]:1'b0)| + ((_net_167)?r2[14]:1'b0)| + ((_net_164)?r2[13]:1'b0)| + ((_net_161)?r2[12]:1'b0)| + ((_net_158)?r2[11]:1'b0)| + ((_net_155)?r2[10]:1'b0)| + ((_net_152)?r2[9]:1'b0)| + ((_net_149)?r2[8]:1'b0)| + ((_net_146)?r2[7]:1'b0)| + ((_net_143)?r2[6]:1'b0)| + ((_net_140)?r2[5]:1'b0)| + ((_net_137)?r2[4]:1'b0)| + ((_net_134)?r2[3]:1'b0)| + ((_net_131)?r2[2]:1'b0)| + ((_net_128)?r2[1]:1'b0)| + ((_net_124)?r2[0]:1'b0)| + ((_net_121)?r1[31]:1'b0)| + ((_net_118)?r1[30]:1'b0)| + ((_net_115)?r1[29]:1'b0)| + ((_net_112)?r1[28]:1'b0)| + ((_net_109)?r1[27]:1'b0)| + ((_net_106)?r1[26]:1'b0)| + ((_net_103)?r1[25]:1'b0)| + ((_net_100)?r1[24]:1'b0)| + ((_net_97)?r1[23]:1'b0)| + ((_net_94)?r1[22]:1'b0)| + ((_net_91)?r1[21]:1'b0)| + ((_net_88)?r1[20]:1'b0)| + ((_net_85)?r1[19]:1'b0)| + ((_net_82)?r1[18]:1'b0)| + ((_net_79)?r1[17]:1'b0)| + ((_net_76)?r1[16]:1'b0)| + ((_net_73)?r1[15]:1'b0)| + ((_net_70)?r1[14]:1'b0)| + ((_net_67)?r1[13]:1'b0)| + ((_net_64)?r1[12]:1'b0)| + ((_net_61)?r1[11]:1'b0)| + ((_net_58)?r1[10]:1'b0)| + ((_net_55)?r1[9]:1'b0)| + ((_net_52)?r1[8]:1'b0)| + ((_net_49)?r1[7]:1'b0)| + ((_net_46)?r1[6]:1'b0)| + ((_net_43)?r1[5]:1'b0)| + ((_net_40)?r1[4]:1'b0)| + ((_net_37)?r1[3]:1'b0)| + ((_net_34)?r1[2]:1'b0)| + ((_net_31)?r1[1]:1'b0)| + ((_net_27)?r1[0]:1'b0); + assign _net_0 = (h_cnt)==(10'b1100100000); + assign _net_1 = (h_cnt)==(10'b1100001110); + assign _net_2 = (h_cnt)==(10'b0010001110); + assign _net_3 = (h_cnt)==(10'b0001100000); + assign _net_4 = (((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3); + assign _net_5 = (v_cnt)==(19'b1100101110000011111); + assign _net_6 = (v_cnt)==(19'b1100011110011011111); + assign _net_7 = (v_cnt)==(19'b0000110000011011111); + assign _net_8 = (v_cnt)==(19'b0000000011000111111); + assign _net_9 = (((~_net_5)&(~_net_6))&(~_net_7))&(~_net_8); + assign _net_10 = hdata_flg&vdata_flg; + assign _net_11 = (((h_cnt) >= ((10'b0010001110)+(10'b1001100001)))&((h_cnt) <= (((10'b1100001110)+(10'b1001100001))+(10'b1111111111))))&((v_cnt) >= ((19'b0000110000011011111)+(19'b1111111111111100001)))&((v_cnt) <= (((19'b1100011110011011111)+(19'b1111111111111100001))+(19'b1111111111111111111))); + assign _net_12 = (bit32_cnt)==(5'b00000); + assign _net_13 = _net_11&_net_12; + assign _net_14 = (bit32_cnt)==(5'b11111); + assign _net_15 = _net_11&_net_14; + assign _net_16 = _net_11&(~_net_14); + assign _net_17 = ~_net_11; + assign _net_18 = hdata_flg&vdata_flg; + assign _net_19 = ~_net_18; + assign _net_20 = ~_net_18; + assign _net_21 = ~_net_18; + assign _net_22 = ack_req_32dot&data_select_flag; + assign _net_23 = ack_req_32dot&(~data_select_flag); + assign _net_24 = ~reg_flg; + assign _net_25 = (bit32_cnt)==(5'b11111); + assign _net_26 = disp_data&_net_24; + assign _net_27 = (disp_data&_net_24)&_net_25; + assign _net_28 = (disp_data&_net_24)&_net_25; + assign _net_29 = (bit32_cnt)==(5'b11110); + assign _net_30 = disp_data&_net_24; + assign _net_31 = (disp_data&_net_24)&_net_29; + assign _net_32 = (bit32_cnt)==(5'b11101); + assign _net_33 = disp_data&_net_24; + assign _net_34 = (disp_data&_net_24)&_net_32; + assign _net_35 = (bit32_cnt)==(5'b11100); + assign _net_36 = disp_data&_net_24; + assign _net_37 = (disp_data&_net_24)&_net_35; + assign _net_38 = (bit32_cnt)==(5'b11011); + assign _net_39 = disp_data&_net_24; + assign _net_40 = (disp_data&_net_24)&_net_38; + assign _net_41 = (bit32_cnt)==(5'b11010); + assign _net_42 = disp_data&_net_24; + assign _net_43 = (disp_data&_net_24)&_net_41; + assign _net_44 = (bit32_cnt)==(5'b11001); + assign _net_45 = disp_data&_net_24; + assign _net_46 = (disp_data&_net_24)&_net_44; + assign _net_47 = (bit32_cnt)==(5'b11000); + assign _net_48 = disp_data&_net_24; + assign _net_49 = (disp_data&_net_24)&_net_47; + assign _net_50 = (bit32_cnt)==(5'b10111); + assign _net_51 = disp_data&_net_24; + assign _net_52 = (disp_data&_net_24)&_net_50; + assign _net_53 = (bit32_cnt)==(5'b10110); + assign _net_54 = disp_data&_net_24; + assign _net_55 = (disp_data&_net_24)&_net_53; + assign _net_56 = (bit32_cnt)==(5'b10101); + assign _net_57 = disp_data&_net_24; + assign _net_58 = (disp_data&_net_24)&_net_56; + assign _net_59 = (bit32_cnt)==(5'b10100); + assign _net_60 = disp_data&_net_24; + assign _net_61 = (disp_data&_net_24)&_net_59; + assign _net_62 = (bit32_cnt)==(5'b10011); + assign _net_63 = disp_data&_net_24; + assign _net_64 = (disp_data&_net_24)&_net_62; + assign _net_65 = (bit32_cnt)==(5'b10010); + assign _net_66 = disp_data&_net_24; + assign _net_67 = (disp_data&_net_24)&_net_65; + assign _net_68 = (bit32_cnt)==(5'b10001); + assign _net_69 = disp_data&_net_24; + assign _net_70 = (disp_data&_net_24)&_net_68; + assign _net_71 = (bit32_cnt)==(5'b10000); + assign _net_72 = disp_data&_net_24; + assign _net_73 = (disp_data&_net_24)&_net_71; + assign _net_74 = (bit32_cnt)==(5'b01111); + assign _net_75 = disp_data&_net_24; + assign _net_76 = (disp_data&_net_24)&_net_74; + assign _net_77 = (bit32_cnt)==(5'b01110); + assign _net_78 = disp_data&_net_24; + assign _net_79 = (disp_data&_net_24)&_net_77; + assign _net_80 = (bit32_cnt)==(5'b01101); + assign _net_81 = disp_data&_net_24; + assign _net_82 = (disp_data&_net_24)&_net_80; + assign _net_83 = (bit32_cnt)==(5'b01100); + assign _net_84 = disp_data&_net_24; + assign _net_85 = (disp_data&_net_24)&_net_83; + assign _net_86 = (bit32_cnt)==(5'b01011); + assign _net_87 = disp_data&_net_24; + assign _net_88 = (disp_data&_net_24)&_net_86; + assign _net_89 = (bit32_cnt)==(5'b01010); + assign _net_90 = disp_data&_net_24; + assign _net_91 = (disp_data&_net_24)&_net_89; + assign _net_92 = (bit32_cnt)==(5'b01001); + assign _net_93 = disp_data&_net_24; + assign _net_94 = (disp_data&_net_24)&_net_92; + assign _net_95 = (bit32_cnt)==(5'b01000); + assign _net_96 = disp_data&_net_24; + assign _net_97 = (disp_data&_net_24)&_net_95; + assign _net_98 = (bit32_cnt)==(5'b00111); + assign _net_99 = disp_data&_net_24; + assign _net_100 = (disp_data&_net_24)&_net_98; + assign _net_101 = (bit32_cnt)==(5'b00110); + assign _net_102 = disp_data&_net_24; + assign _net_103 = (disp_data&_net_24)&_net_101; + assign _net_104 = (bit32_cnt)==(5'b00101); + assign _net_105 = disp_data&_net_24; + assign _net_106 = (disp_data&_net_24)&_net_104; + assign _net_107 = (bit32_cnt)==(5'b00100); + assign _net_108 = disp_data&_net_24; + assign _net_109 = (disp_data&_net_24)&_net_107; + assign _net_110 = (bit32_cnt)==(5'b00011); + assign _net_111 = disp_data&_net_24; + assign _net_112 = (disp_data&_net_24)&_net_110; + assign _net_113 = (bit32_cnt)==(5'b00010); + assign _net_114 = disp_data&_net_24; + assign _net_115 = (disp_data&_net_24)&_net_113; + assign _net_116 = (bit32_cnt)==(5'b00001); + assign _net_117 = disp_data&_net_24; + assign _net_118 = (disp_data&_net_24)&_net_116; + assign _net_119 = (bit32_cnt)==(5'b00000); + assign _net_120 = disp_data&_net_24; + assign _net_121 = (disp_data&_net_24)&_net_119; + assign _net_122 = (bit32_cnt)==(5'b11111); + assign _net_123 = disp_data&(~_net_24); + assign _net_124 = (disp_data&(~_net_24))&_net_122; + assign _net_125 = (disp_data&(~_net_24))&_net_122; + assign _net_126 = (bit32_cnt)==(5'b11110); + assign _net_127 = disp_data&(~_net_24); + assign _net_128 = (disp_data&(~_net_24))&_net_126; + assign _net_129 = (bit32_cnt)==(5'b11101); + assign _net_130 = disp_data&(~_net_24); + assign _net_131 = (disp_data&(~_net_24))&_net_129; + assign _net_132 = (bit32_cnt)==(5'b11100); + assign _net_133 = disp_data&(~_net_24); + assign _net_134 = (disp_data&(~_net_24))&_net_132; + assign _net_135 = (bit32_cnt)==(5'b11011); + assign _net_136 = disp_data&(~_net_24); + assign _net_137 = (disp_data&(~_net_24))&_net_135; + assign _net_138 = (bit32_cnt)==(5'b11010); + assign _net_139 = disp_data&(~_net_24); + assign _net_140 = (disp_data&(~_net_24))&_net_138; + assign _net_141 = (bit32_cnt)==(5'b11001); + assign _net_142 = disp_data&(~_net_24); + assign _net_143 = (disp_data&(~_net_24))&_net_141; + assign _net_144 = (bit32_cnt)==(5'b11000); + assign _net_145 = disp_data&(~_net_24); + assign _net_146 = (disp_data&(~_net_24))&_net_144; + assign _net_147 = (bit32_cnt)==(5'b10111); + assign _net_148 = disp_data&(~_net_24); + assign _net_149 = (disp_data&(~_net_24))&_net_147; + assign _net_150 = (bit32_cnt)==(5'b10110); + assign _net_151 = disp_data&(~_net_24); + assign _net_152 = (disp_data&(~_net_24))&_net_150; + assign _net_153 = (bit32_cnt)==(5'b10101); + assign _net_154 = disp_data&(~_net_24); + assign _net_155 = (disp_data&(~_net_24))&_net_153; + assign _net_156 = (bit32_cnt)==(5'b10100); + assign _net_157 = disp_data&(~_net_24); + assign _net_158 = (disp_data&(~_net_24))&_net_156; + assign _net_159 = (bit32_cnt)==(5'b10011); + assign _net_160 = disp_data&(~_net_24); + assign _net_161 = (disp_data&(~_net_24))&_net_159; + assign _net_162 = (bit32_cnt)==(5'b10010); + assign _net_163 = disp_data&(~_net_24); + assign _net_164 = (disp_data&(~_net_24))&_net_162; + assign _net_165 = (bit32_cnt)==(5'b10001); + assign _net_166 = disp_data&(~_net_24); + assign _net_167 = (disp_data&(~_net_24))&_net_165; + assign _net_168 = (bit32_cnt)==(5'b10000); + assign _net_169 = disp_data&(~_net_24); + assign _net_170 = (disp_data&(~_net_24))&_net_168; + assign _net_171 = (bit32_cnt)==(5'b01111); + assign _net_172 = disp_data&(~_net_24); + assign _net_173 = (disp_data&(~_net_24))&_net_171; + assign _net_174 = (bit32_cnt)==(5'b01110); + assign _net_175 = disp_data&(~_net_24); + assign _net_176 = (disp_data&(~_net_24))&_net_174; + assign _net_177 = (bit32_cnt)==(5'b01101); + assign _net_178 = disp_data&(~_net_24); + assign _net_179 = (disp_data&(~_net_24))&_net_177; + assign _net_180 = (bit32_cnt)==(5'b01100); + assign _net_181 = disp_data&(~_net_24); + assign _net_182 = (disp_data&(~_net_24))&_net_180; + assign _net_183 = (bit32_cnt)==(5'b01011); + assign _net_184 = disp_data&(~_net_24); + assign _net_185 = (disp_data&(~_net_24))&_net_183; + assign _net_186 = (bit32_cnt)==(5'b01010); + assign _net_187 = disp_data&(~_net_24); + assign _net_188 = (disp_data&(~_net_24))&_net_186; + assign _net_189 = (bit32_cnt)==(5'b01001); + assign _net_190 = disp_data&(~_net_24); + assign _net_191 = (disp_data&(~_net_24))&_net_189; + assign _net_192 = (bit32_cnt)==(5'b01000); + assign _net_193 = disp_data&(~_net_24); + assign _net_194 = (disp_data&(~_net_24))&_net_192; + assign _net_195 = (bit32_cnt)==(5'b00111); + assign _net_196 = disp_data&(~_net_24); + assign _net_197 = (disp_data&(~_net_24))&_net_195; + assign _net_198 = (bit32_cnt)==(5'b00110); + assign _net_199 = disp_data&(~_net_24); + assign _net_200 = (disp_data&(~_net_24))&_net_198; + assign _net_201 = (bit32_cnt)==(5'b00101); + assign _net_202 = disp_data&(~_net_24); + assign _net_203 = (disp_data&(~_net_24))&_net_201; + assign _net_204 = (bit32_cnt)==(5'b00100); + assign _net_205 = disp_data&(~_net_24); + assign _net_206 = (disp_data&(~_net_24))&_net_204; + assign _net_207 = (bit32_cnt)==(5'b00011); + assign _net_208 = disp_data&(~_net_24); + assign _net_209 = (disp_data&(~_net_24))&_net_207; + assign _net_210 = (bit32_cnt)==(5'b00010); + assign _net_211 = disp_data&(~_net_24); + assign _net_212 = (disp_data&(~_net_24))&_net_210; + assign _net_213 = (bit32_cnt)==(5'b00001); + assign _net_214 = disp_data&(~_net_24); + assign _net_215 = (disp_data&(~_net_24))&_net_213; + assign _net_216 = (bit32_cnt)==(5'b00000); + assign _net_217 = disp_data&(~_net_24); + assign _net_218 = (disp_data&(~_net_24))&_net_216; + assign v_sync_o = v_sync; + assign h_sync_o = h_sync; + assign vga_red_o = red; + assign vga_green_o = green; + assign vga_blue_o = blue; + assign h_cnt_o = h_cnt; + assign req_32dot = _net_13; +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + v_sync <= 1'b0; +else if ((_net_8|_net_5)) + v_sync <= ~v_sync; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + h_sync <= 1'b0; +else if ((_net_3|_net_0)) + h_sync <= ~h_sync; +end +always @(posedge p_reset) + begin +if (p_reset) + h_flg <= 1'b0; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + vdata_flg <= 1'b0; +else if ((_net_7)|(_net_6)) + vdata_flg <= ((_net_7) ?1'b1:1'b0)| + ((_net_6) ?1'b0:1'b0); + +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + hdata_flg <= 1'b0; +else if ((_net_2)|(_net_1)) + hdata_flg <= ((_net_2) ?1'b1:1'b0)| + ((_net_1) ?1'b0:1'b0); + +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + h_cnt <= 10'b0000000000; +else if ((_net_4|_net_3|_net_2|_net_1)|(_net_0)) + h_cnt <= ((_net_4|_net_3|_net_2|_net_1) ?(h_cnt)+(10'b0000000001):10'b0)| + ((_net_0) ?10'b0000000000:10'b0); + +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + v_cnt <= 19'b0000000000000000000; +else if ((_net_9|_net_8|_net_7|_net_6)|(_net_5)) + v_cnt <= ((_net_9|_net_8|_net_7|_net_6) ?(v_cnt)+(19'b0000000000000000001):19'b0)| + ((_net_5) ?19'b0000000000000000000:19'b0); + +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + bit32_cnt <= 5'b00000; +else if ((disp_data)|(_net_16)|(_net_17|_net_15)) + bit32_cnt <= ((disp_data) ?(bit32_cnt)+(5'b00001):5'b0)| + ((_net_16) ?(bit32_cnt)+(5'b00001):5'b0)| + ((_net_17|_net_15) ?5'b00000:5'b0); + +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + reg_flg <= 1'b0; +else if ((_net_125|_net_28)) + reg_flg <= ~reg_flg; +end +always @(posedge p_reset) + begin +if (p_reset) + reg_cnt <= 1'b0; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + r1 <= 32'b00000000000000000000000000000000; +else if ((_net_22)) + r1 <= pix32_data_i; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + r2 <= 32'b00000000000000000000000000000000; +else if ((_net_23)) + r2 <= pix32_data_i; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + data_select_flag <= 1'b0; +else if ((ack_req_32dot)) + data_select_flag <= ~data_select_flag; +end +endmodule +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:36 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp +*/ diff --git a/VGADisplay/Verilog/vga_top.v b/VGADisplay/Verilog/vga_top.v new file mode 100644 index 0000000..15ddce6 --- /dev/null +++ b/VGADisplay/Verilog/vga_top.v @@ -0,0 +1,875 @@ +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:06:31 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER: +*/ + +module vga_generate ( p_reset , m_clock , pix32_data_i , v_sync_o , h_sync_o , vga_red_o , vga_green_o , vga_blue_o , h_cnt_o , ack_req_32dot , req_32dot ); + input p_reset; + input m_clock; + input [31:0] pix32_data_i; + output v_sync_o; + output h_sync_o; + output [3:0] vga_red_o; + output [3:0] vga_green_o; + output [3:0] vga_blue_o; + output [9:0] h_cnt_o; + input ack_req_32dot; + output req_32dot; + wire disp_data; + reg v_sync; + reg h_sync; + reg h_flg; + reg vdata_flg; + reg hdata_flg; + reg [9:0] h_cnt; + reg [18:0] v_cnt; + reg [4:0] bit32_cnt; + reg reg_flg; + reg reg_cnt; + reg [31:0] r1; + reg [31:0] r2; + reg data_select_flag; + wire [3:0] red; + wire [3:0] green; + wire [3:0] blue; + wire sel_disp_data; + wire _net_0; + wire _net_1; + wire _net_2; + wire _net_3; + wire _net_4; + wire _net_5; + wire _net_6; + wire _net_7; + wire _net_8; + wire _net_9; + wire _net_10; + wire _net_11; + wire _net_12; + wire _net_13; + wire _net_14; + wire _net_15; + wire _net_16; + wire _net_17; + wire _net_18; + wire _net_19; + wire _net_20; + wire _net_21; + wire _net_22; + wire _net_23; + wire _net_24; + wire _net_25; + wire _net_26; + wire _net_27; + wire _net_28; + wire _net_29; + wire _net_30; + wire _net_31; + wire _net_32; + wire _net_33; + wire _net_34; + wire _net_35; + wire _net_36; + wire _net_37; + wire _net_38; + wire _net_39; + wire _net_40; + wire _net_41; + wire _net_42; + wire _net_43; + wire _net_44; + wire _net_45; + wire _net_46; + wire _net_47; + wire _net_48; + wire _net_49; + wire _net_50; + wire _net_51; + wire _net_52; + wire _net_53; + wire _net_54; + wire _net_55; + wire _net_56; + wire _net_57; + wire _net_58; + wire _net_59; + wire _net_60; + wire _net_61; + wire _net_62; + wire _net_63; + wire _net_64; + wire _net_65; + wire _net_66; + wire _net_67; + wire _net_68; + wire _net_69; + wire _net_70; + wire _net_71; + wire _net_72; + wire _net_73; + wire _net_74; + wire _net_75; + wire _net_76; + wire _net_77; + wire _net_78; + wire _net_79; + wire _net_80; + wire _net_81; + wire _net_82; + wire _net_83; + wire _net_84; + wire _net_85; + wire _net_86; + wire _net_87; + wire _net_88; + wire _net_89; + wire _net_90; + wire _net_91; + wire _net_92; + wire _net_93; + wire _net_94; + wire _net_95; + wire _net_96; + wire _net_97; + wire _net_98; + wire _net_99; + wire _net_100; + wire _net_101; + wire _net_102; + wire _net_103; + wire _net_104; + wire _net_105; + wire _net_106; + wire _net_107; + wire _net_108; + wire _net_109; + wire _net_110; + wire _net_111; + wire _net_112; + wire _net_113; + wire _net_114; + wire _net_115; + wire _net_116; + wire _net_117; + wire _net_118; + wire _net_119; + wire _net_120; + wire _net_121; + wire _net_122; + wire _net_123; + wire _net_124; + wire _net_125; + wire _net_126; + wire _net_127; + wire _net_128; + wire _net_129; + wire _net_130; + wire _net_131; + wire _net_132; + wire _net_133; + wire _net_134; + wire _net_135; + wire _net_136; + wire _net_137; + wire _net_138; + wire _net_139; + wire _net_140; + wire _net_141; + wire _net_142; + wire _net_143; + wire _net_144; + wire _net_145; + wire _net_146; + wire _net_147; + wire _net_148; + wire _net_149; + wire _net_150; + wire _net_151; + wire _net_152; + wire _net_153; + wire _net_154; + wire _net_155; + wire _net_156; + wire _net_157; + wire _net_158; + wire _net_159; + wire _net_160; + wire _net_161; + wire _net_162; + wire _net_163; + wire _net_164; + wire _net_165; + wire _net_166; + wire _net_167; + wire _net_168; + wire _net_169; + wire _net_170; + wire _net_171; + wire _net_172; + wire _net_173; + wire _net_174; + wire _net_175; + wire _net_176; + wire _net_177; + wire _net_178; + wire _net_179; + wire _net_180; + wire _net_181; + wire _net_182; + wire _net_183; + wire _net_184; + wire _net_185; + wire _net_186; + wire _net_187; + wire _net_188; + wire _net_189; + wire _net_190; + wire _net_191; + wire _net_192; + wire _net_193; + wire _net_194; + wire _net_195; + wire _net_196; + wire _net_197; + wire _net_198; + wire _net_199; + wire _net_200; + wire _net_201; + wire _net_202; + wire _net_203; + wire _net_204; + wire _net_205; + wire _net_206; + wire _net_207; + wire _net_208; + wire _net_209; + wire _net_210; + wire _net_211; + wire _net_212; + wire _net_213; + wire _net_214; + wire _net_215; + wire _net_216; + wire _net_217; + wire _net_218; + + assign disp_data = _net_10; + assign red = 4'b0000; + assign green = 4'b0000; + assign blue = ((_net_20)?4'b0000:4'b0)| + ((_net_18)?4'b1111:4'b0); + assign sel_disp_data = ((_net_218)?r2[31]:1'b0)| + ((_net_215)?r2[30]:1'b0)| + ((_net_212)?r2[29]:1'b0)| + ((_net_209)?r2[28]:1'b0)| + ((_net_206)?r2[27]:1'b0)| + ((_net_203)?r2[26]:1'b0)| + ((_net_200)?r2[25]:1'b0)| + ((_net_197)?r2[24]:1'b0)| + ((_net_194)?r2[23]:1'b0)| + ((_net_191)?r2[22]:1'b0)| + ((_net_188)?r2[21]:1'b0)| + ((_net_185)?r2[20]:1'b0)| + ((_net_182)?r2[19]:1'b0)| + ((_net_179)?r2[18]:1'b0)| + ((_net_176)?r2[17]:1'b0)| + ((_net_173)?r2[16]:1'b0)| + ((_net_170)?r2[15]:1'b0)| + ((_net_167)?r2[14]:1'b0)| + ((_net_164)?r2[13]:1'b0)| + ((_net_161)?r2[12]:1'b0)| + ((_net_158)?r2[11]:1'b0)| + ((_net_155)?r2[10]:1'b0)| + ((_net_152)?r2[9]:1'b0)| + ((_net_149)?r2[8]:1'b0)| + ((_net_146)?r2[7]:1'b0)| + ((_net_143)?r2[6]:1'b0)| + ((_net_140)?r2[5]:1'b0)| + ((_net_137)?r2[4]:1'b0)| + ((_net_134)?r2[3]:1'b0)| + ((_net_131)?r2[2]:1'b0)| + ((_net_128)?r2[1]:1'b0)| + ((_net_124)?r2[0]:1'b0)| + ((_net_121)?r1[31]:1'b0)| + ((_net_118)?r1[30]:1'b0)| + ((_net_115)?r1[29]:1'b0)| + ((_net_112)?r1[28]:1'b0)| + ((_net_109)?r1[27]:1'b0)| + ((_net_106)?r1[26]:1'b0)| + ((_net_103)?r1[25]:1'b0)| + ((_net_100)?r1[24]:1'b0)| + ((_net_97)?r1[23]:1'b0)| + ((_net_94)?r1[22]:1'b0)| + ((_net_91)?r1[21]:1'b0)| + ((_net_88)?r1[20]:1'b0)| + ((_net_85)?r1[19]:1'b0)| + ((_net_82)?r1[18]:1'b0)| + ((_net_79)?r1[17]:1'b0)| + ((_net_76)?r1[16]:1'b0)| + ((_net_73)?r1[15]:1'b0)| + ((_net_70)?r1[14]:1'b0)| + ((_net_67)?r1[13]:1'b0)| + ((_net_64)?r1[12]:1'b0)| + ((_net_61)?r1[11]:1'b0)| + ((_net_58)?r1[10]:1'b0)| + ((_net_55)?r1[9]:1'b0)| + ((_net_52)?r1[8]:1'b0)| + ((_net_49)?r1[7]:1'b0)| + ((_net_46)?r1[6]:1'b0)| + ((_net_43)?r1[5]:1'b0)| + ((_net_40)?r1[4]:1'b0)| + ((_net_37)?r1[3]:1'b0)| + ((_net_34)?r1[2]:1'b0)| + ((_net_31)?r1[1]:1'b0)| + ((_net_27)?r1[0]:1'b0); + assign _net_0 = (h_cnt)==(10'b1100100000); + assign _net_1 = (h_cnt)==(10'b1100001110); + assign _net_2 = (h_cnt)==(10'b0010001110); + assign _net_3 = (h_cnt)==(10'b0001100000); + assign _net_4 = (((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3); + assign _net_5 = (v_cnt)==(19'b1100101110000011111); + assign _net_6 = (v_cnt)==(19'b1100011110011011111); + assign _net_7 = (v_cnt)==(19'b0000110000011011111); + assign _net_8 = (v_cnt)==(19'b0000000011000111111); + assign _net_9 = (((~_net_5)&(~_net_6))&(~_net_7))&(~_net_8); + assign _net_10 = hdata_flg&vdata_flg; + assign _net_11 = (((h_cnt) >= ((10'b0010001110)+(10'b1001100001)))&((h_cnt) <= (((10'b1100001110)+(10'b1001100001))+(10'b1111111111))))&((v_cnt) >= ((19'b0000110000011011111)+(19'b1111111111111100001)))&((v_cnt) <= (((19'b1100011110011011111)+(19'b1111111111111100001))+(19'b1111111111111111111))); + assign _net_12 = (bit32_cnt)==(5'b00000); + assign _net_13 = _net_11&_net_12; + assign _net_14 = (bit32_cnt)==(5'b11111); + assign _net_15 = _net_11&_net_14; + assign _net_16 = _net_11&(~_net_14); + assign _net_17 = ~_net_11; + assign _net_18 = hdata_flg&vdata_flg; + assign _net_19 = ~_net_18; + assign _net_20 = ~_net_18; + assign _net_21 = ~_net_18; + assign _net_22 = ack_req_32dot&data_select_flag; + assign _net_23 = ack_req_32dot&(~data_select_flag); + assign _net_24 = ~reg_flg; + assign _net_25 = (bit32_cnt)==(5'b11111); + assign _net_26 = disp_data&_net_24; + assign _net_27 = (disp_data&_net_24)&_net_25; + assign _net_28 = (disp_data&_net_24)&_net_25; + assign _net_29 = (bit32_cnt)==(5'b11110); + assign _net_30 = disp_data&_net_24; + assign _net_31 = (disp_data&_net_24)&_net_29; + assign _net_32 = (bit32_cnt)==(5'b11101); + assign _net_33 = disp_data&_net_24; + assign _net_34 = (disp_data&_net_24)&_net_32; + assign _net_35 = (bit32_cnt)==(5'b11100); + assign _net_36 = disp_data&_net_24; + assign _net_37 = (disp_data&_net_24)&_net_35; + assign _net_38 = (bit32_cnt)==(5'b11011); + assign _net_39 = disp_data&_net_24; + assign _net_40 = (disp_data&_net_24)&_net_38; + assign _net_41 = (bit32_cnt)==(5'b11010); + assign _net_42 = disp_data&_net_24; + assign _net_43 = (disp_data&_net_24)&_net_41; + assign _net_44 = (bit32_cnt)==(5'b11001); + assign _net_45 = disp_data&_net_24; + assign _net_46 = (disp_data&_net_24)&_net_44; + assign _net_47 = (bit32_cnt)==(5'b11000); + assign _net_48 = disp_data&_net_24; + assign _net_49 = (disp_data&_net_24)&_net_47; + assign _net_50 = (bit32_cnt)==(5'b10111); + assign _net_51 = disp_data&_net_24; + assign _net_52 = (disp_data&_net_24)&_net_50; + assign _net_53 = (bit32_cnt)==(5'b10110); + assign _net_54 = disp_data&_net_24; + assign _net_55 = (disp_data&_net_24)&_net_53; + assign _net_56 = (bit32_cnt)==(5'b10101); + assign _net_57 = disp_data&_net_24; + assign _net_58 = (disp_data&_net_24)&_net_56; + assign _net_59 = (bit32_cnt)==(5'b10100); + assign _net_60 = disp_data&_net_24; + assign _net_61 = (disp_data&_net_24)&_net_59; + assign _net_62 = (bit32_cnt)==(5'b10011); + assign _net_63 = disp_data&_net_24; + assign _net_64 = (disp_data&_net_24)&_net_62; + assign _net_65 = (bit32_cnt)==(5'b10010); + assign _net_66 = disp_data&_net_24; + assign _net_67 = (disp_data&_net_24)&_net_65; + assign _net_68 = (bit32_cnt)==(5'b10001); + assign _net_69 = disp_data&_net_24; + assign _net_70 = (disp_data&_net_24)&_net_68; + assign _net_71 = (bit32_cnt)==(5'b10000); + assign _net_72 = disp_data&_net_24; + assign _net_73 = (disp_data&_net_24)&_net_71; + assign _net_74 = (bit32_cnt)==(5'b01111); + assign _net_75 = disp_data&_net_24; + assign _net_76 = (disp_data&_net_24)&_net_74; + assign _net_77 = (bit32_cnt)==(5'b01110); + assign _net_78 = disp_data&_net_24; + assign _net_79 = (disp_data&_net_24)&_net_77; + assign _net_80 = (bit32_cnt)==(5'b01101); + assign _net_81 = disp_data&_net_24; + assign _net_82 = (disp_data&_net_24)&_net_80; + assign _net_83 = (bit32_cnt)==(5'b01100); + assign _net_84 = disp_data&_net_24; + assign _net_85 = (disp_data&_net_24)&_net_83; + assign _net_86 = (bit32_cnt)==(5'b01011); + assign _net_87 = disp_data&_net_24; + assign _net_88 = (disp_data&_net_24)&_net_86; + assign _net_89 = (bit32_cnt)==(5'b01010); + assign _net_90 = disp_data&_net_24; + assign _net_91 = (disp_data&_net_24)&_net_89; + assign _net_92 = (bit32_cnt)==(5'b01001); + assign _net_93 = disp_data&_net_24; + assign _net_94 = (disp_data&_net_24)&_net_92; + assign _net_95 = (bit32_cnt)==(5'b01000); + assign _net_96 = disp_data&_net_24; + assign _net_97 = (disp_data&_net_24)&_net_95; + assign _net_98 = (bit32_cnt)==(5'b00111); + assign _net_99 = disp_data&_net_24; + assign _net_100 = (disp_data&_net_24)&_net_98; + assign _net_101 = (bit32_cnt)==(5'b00110); + assign _net_102 = disp_data&_net_24; + assign _net_103 = (disp_data&_net_24)&_net_101; + assign _net_104 = (bit32_cnt)==(5'b00101); + assign _net_105 = disp_data&_net_24; + assign _net_106 = (disp_data&_net_24)&_net_104; + assign _net_107 = (bit32_cnt)==(5'b00100); + assign _net_108 = disp_data&_net_24; + assign _net_109 = (disp_data&_net_24)&_net_107; + assign _net_110 = (bit32_cnt)==(5'b00011); + assign _net_111 = disp_data&_net_24; + assign _net_112 = (disp_data&_net_24)&_net_110; + assign _net_113 = (bit32_cnt)==(5'b00010); + assign _net_114 = disp_data&_net_24; + assign _net_115 = (disp_data&_net_24)&_net_113; + assign _net_116 = (bit32_cnt)==(5'b00001); + assign _net_117 = disp_data&_net_24; + assign _net_118 = (disp_data&_net_24)&_net_116; + assign _net_119 = (bit32_cnt)==(5'b00000); + assign _net_120 = disp_data&_net_24; + assign _net_121 = (disp_data&_net_24)&_net_119; + assign _net_122 = (bit32_cnt)==(5'b11111); + assign _net_123 = disp_data&(~_net_24); + assign _net_124 = (disp_data&(~_net_24))&_net_122; + assign _net_125 = (disp_data&(~_net_24))&_net_122; + assign _net_126 = (bit32_cnt)==(5'b11110); + assign _net_127 = disp_data&(~_net_24); + assign _net_128 = (disp_data&(~_net_24))&_net_126; + assign _net_129 = (bit32_cnt)==(5'b11101); + assign _net_130 = disp_data&(~_net_24); + assign _net_131 = (disp_data&(~_net_24))&_net_129; + assign _net_132 = (bit32_cnt)==(5'b11100); + assign _net_133 = disp_data&(~_net_24); + assign _net_134 = (disp_data&(~_net_24))&_net_132; + assign _net_135 = (bit32_cnt)==(5'b11011); + assign _net_136 = disp_data&(~_net_24); + assign _net_137 = (disp_data&(~_net_24))&_net_135; + assign _net_138 = (bit32_cnt)==(5'b11010); + assign _net_139 = disp_data&(~_net_24); + assign _net_140 = (disp_data&(~_net_24))&_net_138; + assign _net_141 = (bit32_cnt)==(5'b11001); + assign _net_142 = disp_data&(~_net_24); + assign _net_143 = (disp_data&(~_net_24))&_net_141; + assign _net_144 = (bit32_cnt)==(5'b11000); + assign _net_145 = disp_data&(~_net_24); + assign _net_146 = (disp_data&(~_net_24))&_net_144; + assign _net_147 = (bit32_cnt)==(5'b10111); + assign _net_148 = disp_data&(~_net_24); + assign _net_149 = (disp_data&(~_net_24))&_net_147; + assign _net_150 = (bit32_cnt)==(5'b10110); + assign _net_151 = disp_data&(~_net_24); + assign _net_152 = (disp_data&(~_net_24))&_net_150; + assign _net_153 = (bit32_cnt)==(5'b10101); + assign _net_154 = disp_data&(~_net_24); + assign _net_155 = (disp_data&(~_net_24))&_net_153; + assign _net_156 = (bit32_cnt)==(5'b10100); + assign _net_157 = disp_data&(~_net_24); + assign _net_158 = (disp_data&(~_net_24))&_net_156; + assign _net_159 = (bit32_cnt)==(5'b10011); + assign _net_160 = disp_data&(~_net_24); + assign _net_161 = (disp_data&(~_net_24))&_net_159; + assign _net_162 = (bit32_cnt)==(5'b10010); + assign _net_163 = disp_data&(~_net_24); + assign _net_164 = (disp_data&(~_net_24))&_net_162; + assign _net_165 = (bit32_cnt)==(5'b10001); + assign _net_166 = disp_data&(~_net_24); + assign _net_167 = (disp_data&(~_net_24))&_net_165; + assign _net_168 = (bit32_cnt)==(5'b10000); + assign _net_169 = disp_data&(~_net_24); + assign _net_170 = (disp_data&(~_net_24))&_net_168; + assign _net_171 = (bit32_cnt)==(5'b01111); + assign _net_172 = disp_data&(~_net_24); + assign _net_173 = (disp_data&(~_net_24))&_net_171; + assign _net_174 = (bit32_cnt)==(5'b01110); + assign _net_175 = disp_data&(~_net_24); + assign _net_176 = (disp_data&(~_net_24))&_net_174; + assign _net_177 = (bit32_cnt)==(5'b01101); + assign _net_178 = disp_data&(~_net_24); + assign _net_179 = (disp_data&(~_net_24))&_net_177; + assign _net_180 = (bit32_cnt)==(5'b01100); + assign _net_181 = disp_data&(~_net_24); + assign _net_182 = (disp_data&(~_net_24))&_net_180; + assign _net_183 = (bit32_cnt)==(5'b01011); + assign _net_184 = disp_data&(~_net_24); + assign _net_185 = (disp_data&(~_net_24))&_net_183; + assign _net_186 = (bit32_cnt)==(5'b01010); + assign _net_187 = disp_data&(~_net_24); + assign _net_188 = (disp_data&(~_net_24))&_net_186; + assign _net_189 = (bit32_cnt)==(5'b01001); + assign _net_190 = disp_data&(~_net_24); + assign _net_191 = (disp_data&(~_net_24))&_net_189; + assign _net_192 = (bit32_cnt)==(5'b01000); + assign _net_193 = disp_data&(~_net_24); + assign _net_194 = (disp_data&(~_net_24))&_net_192; + assign _net_195 = (bit32_cnt)==(5'b00111); + assign _net_196 = disp_data&(~_net_24); + assign _net_197 = (disp_data&(~_net_24))&_net_195; + assign _net_198 = (bit32_cnt)==(5'b00110); + assign _net_199 = disp_data&(~_net_24); + assign _net_200 = (disp_data&(~_net_24))&_net_198; + assign _net_201 = (bit32_cnt)==(5'b00101); + assign _net_202 = disp_data&(~_net_24); + assign _net_203 = (disp_data&(~_net_24))&_net_201; + assign _net_204 = (bit32_cnt)==(5'b00100); + assign _net_205 = disp_data&(~_net_24); + assign _net_206 = (disp_data&(~_net_24))&_net_204; + assign _net_207 = (bit32_cnt)==(5'b00011); + assign _net_208 = disp_data&(~_net_24); + assign _net_209 = (disp_data&(~_net_24))&_net_207; + assign _net_210 = (bit32_cnt)==(5'b00010); + assign _net_211 = disp_data&(~_net_24); + assign _net_212 = (disp_data&(~_net_24))&_net_210; + assign _net_213 = (bit32_cnt)==(5'b00001); + assign _net_214 = disp_data&(~_net_24); + assign _net_215 = (disp_data&(~_net_24))&_net_213; + assign _net_216 = (bit32_cnt)==(5'b00000); + assign _net_217 = disp_data&(~_net_24); + assign _net_218 = (disp_data&(~_net_24))&_net_216; + assign v_sync_o = v_sync; + assign h_sync_o = h_sync; + assign vga_red_o = red; + assign vga_green_o = green; + assign vga_blue_o = blue; + assign h_cnt_o = h_cnt; + assign req_32dot = _net_13; +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + v_sync <= 1'b0; +else if ((_net_8|_net_5)) + v_sync <= ~v_sync; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + h_sync <= 1'b0; +else if ((_net_3|_net_0)) + h_sync <= ~h_sync; +end +always @(posedge p_reset) + begin +if (p_reset) + h_flg <= 1'b0; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + vdata_flg <= 1'b0; +else if ((_net_7)|(_net_6)) + vdata_flg <= ((_net_7) ?1'b1:1'b0)| + ((_net_6) ?1'b0:1'b0); + +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + hdata_flg <= 1'b0; +else if ((_net_2)|(_net_1)) + hdata_flg <= ((_net_2) ?1'b1:1'b0)| + ((_net_1) ?1'b0:1'b0); + +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + h_cnt <= 10'b0000000000; +else if ((_net_4|_net_3|_net_2|_net_1)|(_net_0)) + h_cnt <= ((_net_4|_net_3|_net_2|_net_1) ?(h_cnt)+(10'b0000000001):10'b0)| + ((_net_0) ?10'b0000000000:10'b0); + +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + v_cnt <= 19'b0000000000000000000; +else if ((_net_9|_net_8|_net_7|_net_6)|(_net_5)) + v_cnt <= ((_net_9|_net_8|_net_7|_net_6) ?(v_cnt)+(19'b0000000000000000001):19'b0)| + ((_net_5) ?19'b0000000000000000000:19'b0); + +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + bit32_cnt <= 5'b00000; +else if ((disp_data)|(_net_16)|(_net_17|_net_15)) + bit32_cnt <= ((disp_data) ?(bit32_cnt)+(5'b00001):5'b0)| + ((_net_16) ?(bit32_cnt)+(5'b00001):5'b0)| + ((_net_17|_net_15) ?5'b00000:5'b0); + +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + reg_flg <= 1'b0; +else if ((_net_125|_net_28)) + reg_flg <= ~reg_flg; +end +always @(posedge p_reset) + begin +if (p_reset) + reg_cnt <= 1'b0; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + r1 <= 32'b00000000000000000000000000000000; +else if ((_net_22)) + r1 <= pix32_data_i; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + r2 <= 32'b00000000000000000000000000000000; +else if ((_net_23)) + r2 <= pix32_data_i; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + data_select_flag <= 1'b0; +else if ((ack_req_32dot)) + data_select_flag <= ~data_select_flag; +end +endmodule +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:06:36 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp +*/ + +module vga_top ( p_reset , m_clock , o_v_sync , o_h_sync , o_red , o_green , o_blue , o_LED ); + input p_reset, m_clock; + output o_v_sync; + output o_h_sync; + output [3:0] o_red; + output [3:0] o_green; + output [3:0] o_blue; + output [7:0] o_LED; + reg r_cnt; + reg [2:0] r_reset; + reg [14:0] r_line_cnt; + reg [13:0] r_line_cnt2; + reg [13:0] r_vram_adrs_cnt; + reg [24:0] r_Sec_cnt; + reg r_Init_flag; + reg [7:0] r_LED; + reg r_test_LED; + reg [7:0] line_buff1 [0:79]; + reg [7:0] line_buff2 [0:79]; + wire fs_vga_sys_init; + wire [14:0] _net_221; + wire _u_VGA_p_reset; + wire _u_VGA_m_clock; + wire [31:0] _u_VGA_pix32_data_i; + wire _u_VGA_v_sync_o; + wire _u_VGA_h_sync_o; + wire [3:0] _u_VGA_vga_red_o; + wire [3:0] _u_VGA_vga_green_o; + wire [3:0] _u_VGA_vga_blue_o; + wire [9:0] _u_VGA_h_cnt_o; + wire _u_VGA_ack_req_32dot; + wire _u_VGA_req_32dot; + wire [13:0] _U_EXP_iRadrs; + wire [15:0] _U_EXP_oRdata; + wire _U_EXP_fiRd_req; + wire _U_EXP_foRd_ack; + wire [7:0] _U_EXP_iWdata; + wire [13:0] _U_EXP_iWadrs; + wire _U_EXP_fiWr_req; + wire _U_EXP_p_reset; + wire _U_EXP_m_clock; + wire _net_222; + wire _net_223; + wire _net_224; + wire _net_225; + wire _net_226; + wire _net_227; + wire _net_228; + wire _net_229; + wire _net_230; + wire _net_231; + wire _net_232; + wire _net_233; + reg _reg_234; + reg _reg_235; + reg _reg_236; + reg _reg_237; + wire _net_238; + wire _reg_235_goto; + wire _net_239; + wire _reg_236_goin; + wire _net_240; + wire _net_241; + wire _reg_236_goto; + wire _net_242; + wire _reg_234_goin; + wire _net_243; + wire _net_244; + wire _net_245; + wire _net_246; + wire _net_247; + wire _net_248; + wire _net_249; + wire _net_250; +exp_ctrl U_EXP (.p_reset(p_reset), .m_clock(m_clock), .fiWr_req(_U_EXP_fiWr_req), .iWadrs(_U_EXP_iWadrs), .iWdata(_U_EXP_iWdata), .foRd_ack(_U_EXP_foRd_ack), .fiRd_req(_U_EXP_fiRd_req), .oRdata(_U_EXP_oRdata), .iRadrs(_U_EXP_iRadrs)); +vga_generate u_VGA (.req_32dot(_u_VGA_req_32dot), .ack_req_32dot(_u_VGA_ack_req_32dot), .h_cnt_o(_u_VGA_h_cnt_o), .vga_blue_o(_u_VGA_vga_blue_o), .vga_green_o(_u_VGA_vga_green_o), .vga_red_o(_u_VGA_vga_red_o), .h_sync_o(_u_VGA_h_sync_o), .v_sync_o(_u_VGA_v_sync_o), .pix32_data_i(_u_VGA_pix32_data_i), .m_clock(_u_VGA_m_clock), .p_reset(_u_VGA_p_reset)); + + assign fs_vga_sys_init = _net_222; + assign _net_221 = (r_line_cnt)+(15'b000000000000001); + assign _u_VGA_p_reset = r_reset[2]; + assign _u_VGA_m_clock = r_cnt; + assign _u_VGA_pix32_data_i = 32'b11111111111111111111111111111111; + assign _u_VGA_ack_req_32dot = _u_VGA_req_32dot; + assign _U_EXP_iRadrs = r_line_cnt2; + assign _U_EXP_fiRd_req = _net_224; + assign _U_EXP_iWdata = 8'b11110000; + assign _U_EXP_iWadrs = r_line_cnt[13:0]; + assign _U_EXP_fiWr_req = _net_244; + assign _net_222 = (r_reset)==(3'b100); + assign _net_223 = (r_Sec_cnt)==(25'b0111110101111000010000000); + assign _net_224 = r_Init_flag&_net_223; + assign _net_225 = r_Init_flag&_net_223; + assign _net_226 = r_Init_flag&_net_223; + assign _net_227 = r_Init_flag&_net_223; + assign _net_228 = (r_line_cnt2)==(14'b00001111101000); + assign _net_229 = r_Init_flag&_net_223; + assign _net_230 = (r_Init_flag&_net_223)&_net_228; + assign _net_231 = (r_Init_flag&_net_223)&(~_net_228); + assign _net_232 = r_Init_flag&(~_net_223); + assign _net_233 = ~r_Init_flag; + assign _net_238 = (_net_221) < (15'b100000000000000); + assign _reg_235_goto = _net_239; + assign _net_239 = _reg_235&_net_238; + assign _reg_236_goin = _net_240; + assign _net_240 = _reg_235&_net_238; + assign _net_241 = ~((r_line_cnt) < (15'b100000000000000)); + assign _reg_236_goto = _net_242; + assign _net_242 = _reg_236&_net_241; + assign _reg_234_goin = _net_243; + assign _net_243 = _reg_236&_net_241; + assign _net_244 = _reg_236&(~_net_241); + assign _net_245 = _reg_236&(~_net_241); + assign _net_246 = _reg_236&(~_net_241); + assign _net_247 = fs_vga_sys_init|_reg_237; + assign _net_248 = (_reg_236_goin|fs_vga_sys_init)|_reg_236|_reg_237; + assign _net_249 = (_reg_236_goin|fs_vga_sys_init)|_reg_235|_reg_236; + assign _net_250 = _reg_234_goin|_reg_234|_reg_235; + assign o_v_sync = _u_VGA_v_sync_o; + assign o_h_sync = _u_VGA_h_sync_o; + assign o_red = _u_VGA_vga_red_o; + assign o_green = _u_VGA_vga_green_o; + assign o_blue = _u_VGA_vga_blue_o; + assign o_LED = r_LED; +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + r_cnt <= 1'b0; +else r_cnt <= ~r_cnt; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + r_reset <= 3'b111; +else r_reset <= {r_reset[1:0],1'b0}; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + r_line_cnt <= 15'b000000000000000; +else if ((_net_247)|(_reg_235)) + r_line_cnt <= ((_net_247) ?15'b000000000000000:15'b0)| + ((_reg_235) ?_net_221:15'b0); + +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + r_line_cnt2 <= 14'b00000000000000; +else if ((_net_231)|(_net_230)) + r_line_cnt2 <= ((_net_231) ?(r_line_cnt2)+(14'b00000000000001):14'b0)| + ((_net_230) ?14'b00000000000000:14'b0); + +end +always @(posedge p_reset) + begin +if (p_reset) + r_vram_adrs_cnt <= 14'b00000000000000; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + r_Sec_cnt <= 25'b0000000000000000000000000; +else if ((_net_232)|(_net_233|_net_226)) + r_Sec_cnt <= ((_net_232) ?(r_Sec_cnt)+(25'b0000000000000000000000001):25'b0)| + ((_net_233|_net_226) ?25'b0000000000000000000000000:25'b0); + +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + r_Init_flag <= 1'b0; +else if ((_reg_234)) + r_Init_flag <= 1'b1; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + r_LED <= 8'b00000000; +else if ((_U_EXP_foRd_ack)) + r_LED <= {_U_EXP_oRdata[10],_U_EXP_oRdata[8],_U_EXP_oRdata[6],_U_EXP_oRdata[4],_U_EXP_oRdata[2],_U_EXP_oRdata[0],r_test_LED,r_Init_flag}; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + r_test_LED <= 1'b0; +else if ((_net_227)) + r_test_LED <= ~r_test_LED; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + _reg_234 <= 1'b0; +else if ((_net_250)) + _reg_234 <= _reg_234_goin|(_reg_235&(~_reg_235_goto)); +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + _reg_235 <= 1'b0; +else if ((_net_249)) + _reg_235 <= _reg_236&(~_reg_236_goto); +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + _reg_236 <= 1'b0; +else if ((_net_248)) + _reg_236 <= (_reg_236_goin|_reg_237)|fs_vga_sys_init; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + _reg_237 <= 1'b0; +else if ((_reg_237)) + _reg_237 <= 1'b0; +end +endmodule +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:06:37 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp +*/ diff --git a/VGADisplay/Verilog/vram.v b/VGADisplay/Verilog/vram.v new file mode 100644 index 0000000..0f4ffe8 --- /dev/null +++ b/VGADisplay/Verilog/vram.v @@ -0,0 +1,34 @@ +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:26 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER: +*/ + +module vram ( clock , data , rdaddress , wraddress , wren , q ); + input clock; + input [7:0] data; + input [13:0] rdaddress; + input [13:0] wraddress; + input wren; + input rden; + output [7:0] q; + reg [7:0] m_vram [0:16383]; + reg [7:0] r_ram_data; + + assign q = r_ram_data; +always @(posedge m_clock) + begin + if (wren) + m_vram[wraddress] <= data; +end + +always @(posedge m_clock) +begin + if (rden) + r_ram_data <= m_vram[rdaddress]; +end + +endmodule +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:26 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp +*/ diff --git a/VGADisplay/Verilog/vram_ctrl.v b/VGADisplay/Verilog/vram_ctrl.v new file mode 100644 index 0000000..bdd4387 --- /dev/null +++ b/VGADisplay/Verilog/vram_ctrl.v @@ -0,0 +1,65 @@ +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:02:20 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER: +*/ + +module vram_ctrl ( p_reset , m_clock , i_Wdata , i_Wadrs , i_Radrs , o_Rdata , fi_Wr_req , fi_Rd_req , fo_Rd_ack ); + input p_reset, m_clock; + input [7:0] i_Wdata; + input [13:0] i_Wadrs; + input [13:0] i_Radrs; + output [7:0] o_Rdata; + input fi_Wr_req; + input fi_Rd_req; + output fo_Rd_ack; + reg [13:0] r_Radrs_hld; + wire _u_VRAM_clk; + wire [7:0] _u_VRAM_d; + wire [13:0] _u_VRAM_ra; + wire [13:0] _u_VRAM_wa; + wire _u_VRAM_we; + wire [7:0] _u_VRAM_q; + wire _u_VRAM_p_reset; + wire _u_VRAM_m_clock; + wire _net_0; + reg _reg_1; + reg _reg_2; + wire _net_3; + wire _net_4; +vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .we(_u_VRAM_we), .wa(_u_VRAM_wa), .ra(_u_VRAM_ra), .d(_u_VRAM_d), .clk(_u_VRAM_clk)); + + assign _u_VRAM_d = i_Wdata; + assign _u_VRAM_ra = ((_net_3)?i_Radrs:14'b0)| + ((_reg_1)?r_Radrs_hld:14'b0); + assign _u_VRAM_wa = i_Wadrs; + assign _u_VRAM_we = fi_Wr_req| + ((_net_0)?1'b0:1'b0); + assign _net_0 = ~fi_Wr_req; + assign _net_3 = fi_Rd_req|_reg_2; + assign _net_4 = fi_Rd_req|_reg_1|_reg_2; + assign o_Rdata = _u_VRAM_q; + assign fo_Rd_ack = _reg_1; +always @(posedge p_reset) + begin +if (p_reset) + r_Radrs_hld <= 14'b00000000000000; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + _reg_1 <= 1'b0; +else if ((_net_4)) + _reg_1 <= _reg_2|fi_Rd_req; +end +always @(posedge m_clock or posedge p_reset) + begin +if (p_reset) + _reg_2 <= 1'b0; +else if ((_reg_2)) + _reg_2 <= 1'b0; +end +endmodule +/* + Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:02:22 2011 + Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp +*/ diff --git a/VGADisplay/src/exp_ctrl.nsh b/VGADisplay/src/exp_ctrl.nsh new file mode 100644 index 0000000..85a9645 --- /dev/null +++ b/VGADisplay/src/exp_ctrl.nsh @@ -0,0 +1,10 @@ +declare exp_ctrl { + input iRadrs[14] ; + output oRdata[16] ; + func_in fiRd_req( iRadrs ) ; + func_out foRd_ack( oRdata ) ; + + input iWdata[8] ; + input iWadrs[14] ; + func_in fiWr_req( iWadrs, iWdata ) ; +} diff --git a/VGADisplay/src/exp_ctrl.nsl b/VGADisplay/src/exp_ctrl.nsl index 362736d..0aaae80 100644 --- a/VGADisplay/src/exp_ctrl.nsl +++ b/VGADisplay/src/exp_ctrl.nsl @@ -3,40 +3,38 @@ #include "vram_ctrl.nsl" declare exp_ctrl { - input iRadrs[14] ; - output oRdata[16] ; - func_in fiRd_req( iRadrs ) ; - func_out foRd_ack( oRdata ) ; + input i_Radrs[14] ; + output o_Rdata[16] ; + func_in fi_Rd_req( i_Radrs ) ; + func_out fo_Rd_ack( o_Rdata ) ; - input iWdata[8] ; - input iWadrs[14] ; - func_in fiWr_req( iWadrs, iWdata ) ; + input i_Wdata[8] ; + input i_Wadrs[14] ; + func_in fi_Wr_req( i_Wadrs, i_Wdata ) ; } module exp_ctrl { - wire exp_q[16] ; - vram_ctrl U_VRAMC ; - - U_VRAMC.p_reset = 0b0 ; - - exp_q = { - U_VRAMC.oRdata[7], U_VRAMC.oRdata[7], - U_VRAMC.oRdata[6], U_VRAMC.oRdata[6], - U_VRAMC.oRdata[5], U_VRAMC.oRdata[5], - U_VRAMC.oRdata[4], U_VRAMC.oRdata[4], - U_VRAMC.oRdata[3], U_VRAMC.oRdata[3], - U_VRAMC.oRdata[2], U_VRAMC.oRdata[2], - U_VRAMC.oRdata[1], U_VRAMC.oRdata[1], - U_VRAMC.oRdata[0], U_VRAMC.oRdata[0] + wire w_exp_q[16] ; + vram_ctrl u_VRAMC ; + + w_exp_q = { + u_VRAMC.o_Rdata[7], u_VRAMC.o_Rdata[7], + u_VRAMC.o_Rdata[6], u_VRAMC.o_Rdata[6], + u_VRAMC.o_Rdata[5], u_VRAMC.o_Rdata[5], + u_VRAMC.o_Rdata[4], u_VRAMC.o_Rdata[4], + u_VRAMC.o_Rdata[3], u_VRAMC.o_Rdata[3], + u_VRAMC.o_Rdata[2], u_VRAMC.o_Rdata[2], + u_VRAMC.o_Rdata[1], u_VRAMC.o_Rdata[1], + u_VRAMC.o_Rdata[0], u_VRAMC.o_Rdata[0] } ; - if( U_VRAMC.foRd_ack ) foRd_ack( exp_q ) ; + if( u_VRAMC.fo_Rd_ack ) fo_Rd_ack( w_exp_q ) ; - func fiRd_req seq { - U_VRAMC.fiRd_req( iRadrs ) ; + func fi_Rd_req seq { + u_VRAMC.fi_Rd_req( i_Radrs ) ; } - func fiWr_req { - U_VRAMC.fiWr_req( iWadrs, iWdata ) ; + func fi_Wr_req { + u_VRAMC.fi_Wr_req( i_Wadrs, i_Wdata ) ; } } \ No newline at end of file diff --git a/VGADisplay/src/vga_top.nsl b/VGADisplay/src/vga_top.nsl index 83fe482..62791b4 100644 --- a/VGADisplay/src/vga_top.nsl +++ b/VGADisplay/src/vga_top.nsl @@ -1,3 +1,11 @@ +/** +* VGA top module +* module name is "vga_top" +* @author zyanham +* @version 1.0 +* comment : +*/ + #define SIM #include "vga_generate.nsl" @@ -8,58 +16,58 @@ declare vga_top { - output v_sync_o ; - output h_sync_o ; - output vga_red_o[4] ; - output vga_green_o[4] ; - output vga_blue_o[4] ; + output o_v_sync ; + output o_h_sync ; + output o_red[4] ; + output o_green[4] ; + output o_blue[4] ; - output oLED[8] ; + output o_LED[8] ; } module vga_top { integer i ; - reg cnt = 0 ; - reg reset[3] = 0b111 ; - reg line_cnt[15] = 0 ; - reg line_cnt2[14] = 0 ; + reg r_cnt = 0 ; + reg r_reset[3] = 0b111 ; + reg r_line_cnt[15] = 0 ; + reg r_line_cnt2[14] = 0 ; - reg vram_adrs_cnt[14] = 0 ; - reg rSec_cnt[25] = 0 ; - reg rInit_flag = 0 ; - reg rLED[8] = 0 ; - reg test_LED = 0 ; + reg r_vram_adrs_cnt[14] = 0 ; + reg r_Sec_cnt[25] = 0 ; + reg r_Init_flag = 0 ; + reg r_LED[8] = 0 ; + reg r_test_LED = 0 ; mem line_buff1[80][8] ; mem line_buff2[80][8] ; - func_self vga_sys_init ; + func_self fs_vga_sys_init ; - vga_generate U_VGA ; - exp_ctrl U_EXP ; + vga_generate u_VGA ; + exp_ctrl U_EXP ; - v_sync_o = U_VGA.v_sync_o ; - h_sync_o = U_VGA.h_sync_o ; - vga_red_o = U_VGA.vga_red_o ; - vga_green_o = U_VGA.vga_green_o ; - vga_blue_o = U_VGA.vga_blue_o ; + o_v_sync = u_VGA.v_sync_o ; + o_h_sync = u_VGA.h_sync_o ; + o_red = u_VGA.vga_red_o ; + o_green = u_VGA.vga_green_o ; + o_blue = u_VGA.vga_blue_o ; - if( U_VGA.req_32dot ) { - U_VGA.ack_req_32dot( 32'hFFFFFFFF ) ; + if( u_VGA.req_32dot ) { + u_VGA.ack_req_32dot( 32'hFFFFFFFF ) ; } { - cnt := ~cnt ; - oLED = rLED ; + r_cnt := ~r_cnt ; + o_LED = r_LED ; - reset := { reset[1:0], 0b0 } ; - if( reset == 0b100 ) vga_sys_init() ; + r_reset := { r_reset[1:0], 0b0 } ; + if( r_reset == 0b100 ) fs_vga_sys_init() ; - U_VGA.p_reset = reset[2] ; - U_VGA.m_clock = cnt ; + u_VGA.p_reset = r_reset[2] ; + u_VGA.m_clock = r_cnt ; if( U_EXP.foRd_ack ) { - rLED := { + r_LED := { // U_EXP.oRdata[14], // U_EXP.oRdata[12], U_EXP.oRdata[10], @@ -68,42 +76,37 @@ module vga_top { U_EXP.oRdata[4], U_EXP.oRdata[2], U_EXP.oRdata[0], - test_LED, - - rInit_flag + r_test_LED, + r_Init_flag } ; } - if( rInit_flag ) { + if( r_Init_flag ) { any { - rSec_cnt == ONE_SEC : { - U_EXP.fiRd_req( line_cnt2 ) ; - rSec_cnt := 0 ; - test_LED := ~test_LED ; + r_Sec_cnt == ONE_SEC : { + U_EXP.fiRd_req( r_line_cnt2 ) ; + r_Sec_cnt := 0 ; + r_test_LED := ~r_test_LED ; any { - line_cnt2 == 14'd1000 : line_cnt2 := 0 ; - else : line_cnt2++ ; + r_line_cnt2 == 14'd1000 : r_line_cnt2 := 0 ; + else : r_line_cnt2++ ; } } else : { - rSec_cnt++ ; + r_Sec_cnt++ ; } } } else { - rSec_cnt := 0 ; + r_Sec_cnt := 0 ; } } - func vga_sys_init seq { -// for(line_cnt=0;line_cnt<80;line_cnt++) { -// line_buff1[line_cnt] := -// } - - for( line_cnt:=0; line_cnt<16384; line_cnt++ ) { - U_EXP.fiWr_req( line_cnt[13:0], line_cnt[7:0] ) ; + func fs_vga_sys_init seq { + for( r_line_cnt:=0; r_line_cnt<16384; r_line_cnt++ ) { + U_EXP.fiWr_req( r_line_cnt[13:0], 8'b11110000 ) ; ; } - rInit_flag := 1 ; + r_Init_flag := 1 ; } } \ No newline at end of file diff --git a/VGADisplay/src/vram.nsh b/VGADisplay/src/vram.nsh index baa373d..a22343e 100644 --- a/VGADisplay/src/vram.nsh +++ b/VGADisplay/src/vram.nsh @@ -1,11 +1,15 @@ -/* VRAM Header File For Altera Config */ - +/** +* VRAM Header File For Altera Config +* Module name is "vram" +* @author zyanham +* @version 1.0 +* comment : Hokuto Ujou Danjin Ken! +*/ declare vram { - input clock ; - input data[8] ; - input rdaddress[14] ; - input wraddress[14] ; - input rden ; - input wren ; + input clk ; + input d[8] ; + input ra[14] ; + input wa[14] ; + input we ; output q[8] ; -} +} \ No newline at end of file diff --git a/VGADisplay/src/vram.nsl b/VGADisplay/src/vram.nsl new file mode 100644 index 0000000..068b94b --- /dev/null +++ b/VGADisplay/src/vram.nsl @@ -0,0 +1,26 @@ +/* VRAM@Module For Simulation */ + +declare vram { + input clock ; + input data[8] ; + input rdaddress[14] ; + input wraddress[14] ; + input wren ; + output q[8] ; +} + +module vram { + mem m_vram[16384][8] ; + reg r_ram_data[8] = 0 ; + + { + /* Write part */ + if(wren) { + m_vram[wraddress] := data ; + } + + /* Read part */ + q = r_ram_data ; + r_ram_data := m_vram[rdaddress] ; + } +} \ No newline at end of file diff --git a/VGADisplay/src/vram_ctrl.nsl b/VGADisplay/src/vram_ctrl.nsl index fc8c305..b6d3221 100644 --- a/VGADisplay/src/vram_ctrl.nsl +++ b/VGADisplay/src/vram_ctrl.nsl @@ -1,45 +1,48 @@ -/* VRAM Control Module */ +/** +* VRAM Control Module +* Module name is "vram_ctrl" +* @author zyanham +* @version 1.0 +* Comment : Reading Steiner +*/ #include "vram.nsh" declare vram_ctrl { - input iWdata[8] ; // in Write Data - input iWadrs[14] ; // in Write Address - input iRadrs[14] ; // in Read Address - output oRdata[8] ; // out Read Data + input i_Wdata[8] ; // in Write Data + input i_Wadrs[14] ; // in Write Address + input i_Radrs[14] ; // in Read Address + output o_Rdata[8] ; // out Read Data - func_in fiWr_req( iWadrs, iWdata ) ; - func_in fiRd_req( iRadrs ) ; - func_out foRd_ack( oRdata ) ; + func_in fi_Wr_req( i_Wadrs, i_Wdata ) ; + func_in fi_Rd_req( i_Radrs ) ; + func_out fo_Rd_ack( o_Rdata ) ; } module vram_ctrl{ - vram U_VRAM ; + vram u_VRAM ; - reg rRadrs_hld[14] = 0 ; + reg r_Radrs_hld[14] = 0 ; { /* Memory Terminal Assign */ - if(~fiWr_req) { - U_VRAM.wren = 0 ; + if(~fi_Wr_req) { + u_VRAM.we = 0 ; } } - func fiWr_req { - U_VRAM.wren = 1 ; - U_VRAM.data = iWdata ; - U_VRAM.wraddress = iWadrs ; + func fi_Wr_req { + u_VRAM.we = 1 ; + u_VRAM.d = i_Wdata ; + u_VRAM.wa = i_Wadrs ; } - func fiRd_req seq { + func fi_Rd_req seq { + u_VRAM.ra = i_Radrs ; { - U_VRAM.rdaddress = iRadrs ; - - } - { - U_VRAM.rdaddress = rRadrs_hld ; - foRd_ack( U_VRAM.q ) ; + u_VRAM.ra = r_Radrs_hld ; + fo_Rd_ack( u_VRAM.q ) ; } } } \ No newline at end of file -- 2.11.0