From 8f97e221d64d76b8c80b5fa6b41a9a77b8ab1c9f Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Fri, 25 Sep 2020 14:34:40 +0800 Subject: [PATCH] drm/amd/pm: correct pcie spc cap setup Correct Polaris10 pcie spc cap setting. Signed-off-by: Evan Quan Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c index 7eca860236db..59c199cd7aeb 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c @@ -2865,6 +2865,8 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) data->pcie_gen_cap = adev->pm.pcie_gen_mask; if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) data->pcie_spc_cap = 20; + else + data->pcie_spc_cap = 16; data->pcie_lane_cap = adev->pm.pcie_mlw_mask; hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ -- 2.11.0