From 901e48e0899a1a6178c8bcb01090a7f9de9cc1a1 Mon Sep 17 00:00:00 2001 From: "K.Ohta" Date: Mon, 8 Apr 2019 17:42:20 +0900 Subject: [PATCH] [VM][PC9801] Improve some registers. --- source/src/vm/pc9801/cpureg.cpp | 21 ++++++++------ source/src/vm/pc9801/cpureg.h | 5 ++++ source/src/vm/pc9801/display.cpp | 29 +++++++++++++++++-- source/src/vm/pc9801/display.h | 1 + source/src/vm/pc9801/membus.cpp | 57 ++++++++++++++++++++++++++++++++++++-- source/src/vm/pc9801/pc9801.cpp | 10 +++++-- source/src/vm/pc9801/pc9801.h | 4 ++- source/src/vm/pc9801/sasi_bios.cpp | 6 ++-- source/src/vm/upd7220.h | 2 -- 9 files changed, 113 insertions(+), 22 deletions(-) diff --git a/source/src/vm/pc9801/cpureg.cpp b/source/src/vm/pc9801/cpureg.cpp index 769a4a8b6..9d89cb31a 100644 --- a/source/src/vm/pc9801/cpureg.cpp +++ b/source/src/vm/pc9801/cpureg.cpp @@ -18,6 +18,7 @@ #else #include "../i286.h" #endif +#include "../i8255.h" namespace PC9801 { @@ -38,14 +39,17 @@ void CPUREG::write_io8(uint32_t addr, uint32_t data) nmi_enabled = true; break; case 0x00f0: - d_cpu->reset(); - d_cpu->set_address_mask(0x000fffff); - //d_mem->reset(); + { + uint8_t reset_reg = d_pio->read_signal(SIG_I8255_PORT_C); + reset_reg = reset_reg & (uint8_t)(~0x20); // Reset SHUT1 + d_pio->write_signal(SIG_I8255_PORT_C, reset_reg, 0xff); + d_cpu->set_address_mask(0x000fffff); + d_cpu->reset(); + } break; case 0x00f2: #if defined(SUPPORT_32BIT_ADDRESS) d_cpu->set_address_mask(0xffffffff); - //d_cpu->set_address_mask(0x00ffffff); #else d_cpu->set_address_mask(0x00ffffff); #endif @@ -80,12 +84,13 @@ uint32_t CPUREG::read_io8(uint32_t addr) // value |= 0x80; // 1 = PC-9821Xt, 0 = PC-9821Xa // value |= 0x80; // CPU MODE, 1 = High/Low, 0 = Middle (PC-9821Ap/As/Ae/Af) // value |= 0x40; // ODP, 1 = Existing (PC-9821Ts) -#if defined(SUPPORT_SCSI_IF) -// value |= 0x40; // Internal 55-type SCSI-HDD, 0 = Existing +#if !defined(SUPPORT_SCSI_IF) + value |= 0x40; // Internal 55-type SCSI-HDD, 0 = Existing #endif -#if defined(SUPPORT_SASI_IF) -// value |= 0x20; // Internal 27-type SASI-HDD, 0 = Existing +#if !defined(SUPPORT_SASI_IF) + value |= 0x20; // Internal 27-type SASI-HDD, 0 = Existing #endif + // ToDo: AMD98 // value |= 0x10; // Unknown value |= ((d_mem->read_signal(SIG_LAST_ACCESS_INTERAM) != 0) ? 0x00: 0x08); // RAM access, 1 = Internal-standard/External-enhanced RAM, 0 = Internal-enhanced RAM // value |= 0x04; // Refresh mode, 1 = Standard, 0 = High speed diff --git a/source/src/vm/pc9801/cpureg.h b/source/src/vm/pc9801/cpureg.h index 28246abec..3b0d8bd88 100644 --- a/source/src/vm/pc9801/cpureg.h +++ b/source/src/vm/pc9801/cpureg.h @@ -35,6 +35,7 @@ private: I286 *d_cpu; #endif DEVICE* d_mem; + DEVICE* d_pio; bool nmi_enabled; public: @@ -63,6 +64,10 @@ public: { d_mem = device; } + void set_context_piosys(DEVICE* device) + { + d_pio = device; + } }; } diff --git a/source/src/vm/pc9801/display.cpp b/source/src/vm/pc9801/display.cpp index 4dcb64cb0..2b458f03b 100644 --- a/source/src/vm/pc9801/display.cpp +++ b/source/src/vm/pc9801/display.cpp @@ -151,7 +151,7 @@ void DISPLAY::initialize() memset(font, 0xff, sizeof(font)); FILEIO* fio = new FILEIO(); - + b_gfx_ff = false; // Q: Is latched beyond resetting? #if !defined(SUPPORT_HIRESO) uint8_t *p = font + 0x81000; uint8_t *q = font + 0x83000; @@ -430,7 +430,29 @@ void DISPLAY::write_io8(uint32_t addr, uint32_t data) crtv = 1; break; case 0x68: - modereg1[(data >> 1) & 7] = data & 1; + switch((data >> 1) & 7) { // From MAME 0.208 + // Related information: + /* + TODO: this is my best bet so far. Register 4 is annoying, the pattern seems to be: + Write to video FF register Graphic -> 00 + Write to video FF register 200 lines -> 0x + Write to video FF register 200 lines -> 00 + + where x is the current mode. + */ + case 1: + b_gfx_ff = true; + break; + case 4: + if(b_gfx_ff) { + modereg1[(data >> 1) & 7] = data & 1; + b_gfx_ff = false; + } + break; + default: + modereg1[(data >> 1) & 7] = data & 1; + break; + } break; #if defined(SUPPORT_16_COLORS) case 0x6a: @@ -2595,7 +2617,7 @@ void DISPLAY::draw_gfx_screen() } } -#define STATE_VERSION 3 +#define STATE_VERSION 4 bool DISPLAY::process_state(FILEIO* state_fio, bool loading) { @@ -2669,6 +2691,7 @@ bool DISPLAY::process_state(FILEIO* state_fio, bool loading) state_fio->StateValue(font_code); state_fio->StateValue(font_line); // state_fio->StateValue(font_lr); + state_fio->StateValue(b_gfx_ff); // post process #if defined(SUPPORT_2ND_VRAM) && !defined(SUPPORT_HIRESO) diff --git a/source/src/vm/pc9801/display.h b/source/src/vm/pc9801/display.h index 6d1edec4f..c27654053 100644 --- a/source/src/vm/pc9801/display.h +++ b/source/src/vm/pc9801/display.h @@ -137,6 +137,7 @@ private: uint16_t font_code; uint8_t font_line; // uint16_t font_lr; + bool b_gfx_ff; uint8_t screen_chr[SCREEN_HEIGHT][SCREEN_WIDTH + 1]; uint8_t screen_gfx[SCREEN_HEIGHT][SCREEN_WIDTH]; diff --git a/source/src/vm/pc9801/membus.cpp b/source/src/vm/pc9801/membus.cpp index 2fe07ff23..4e27bb734 100644 --- a/source/src/vm/pc9801/membus.cpp +++ b/source/src/vm/pc9801/membus.cpp @@ -628,7 +628,11 @@ void MEMBUS::update_bios() // set_memory_mapped_io_rw(0xe0000, 0xe7fff, d_display); // #endif //} - #if defined(SUPPORT_32BIT_ADDRESS) + #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS) + // ToDo: PC9821 + unset_memory_rw(0x00f00000, 0x00f9ffff); + #endif + #if defined(SUPPORT_32BIT_ADDRESS) /*|| defined(SUPPORT_24BIT_ADDRESS)*/ #if !defined(SUPPORT_HIRESO) unset_memory_rw(0xa0000, 0xbffff); set_memory_mapped_io_rw(0xa0000, 0xbffff, d_display); @@ -654,23 +658,38 @@ void MEMBUS::update_bios() update_ide_bios(); #endif } - #endif #endif unset_memory_rw(0x100000 - sizeof(bios), 0xfffff); +#if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS) + // ToDo: PC9821 + unset_memory_rw(0x01000000 - sizeof(bios), 0x00ffffff); +#endif #if defined(SUPPORT_ITF_ROM) if(itf_selected) { set_memory_r(0x100000 - sizeof(itf), 0xfffff, itf); + #if defined(SUPPORT_32BIT_ADDRESS) + set_memory_r(0x01000000 - sizeof(itf), 0x00ffffff, itf); + #endif } else { #endif #if defined(SUPPORT_BIOS_RAM) if(bios_ram_selected) { set_memory_rw(0x100000 - sizeof(bios_ram), 0xfffff, bios_ram); + #if defined(SUPPORT_32BIT_ADDRESS) + set_memory_rw(0x01000000 - sizeof(bios_ram), 0x00ffffff, bios_ram); + #endif } else { #endif set_memory_r(0x100000 - sizeof(bios), 0xfffff, bios); +#if defined(SUPPORT_32BIT_ADDRESS) + set_memory_r(0x01000000 - sizeof(bios), 0x00ffffff, bios); +#endif #if defined(SUPPORT_BIOS_RAM) set_memory_w(0x100000 - sizeof(bios_ram), 0xfffff, bios_ram); + #if defined(SUPPORT_32BIT_ADDRESS) + set_memory_w(0x01000000 - sizeof(bios_ram), 0x00ffffff, bios_ram); + #endif } #endif #if defined(SUPPORT_ITF_ROM) @@ -687,9 +706,16 @@ void MEMBUS::update_sound_bios() // } else { set_memory_r(0xcc000, 0xcffff, sound_bios); unset_memory_w(0xcc000, 0xcffff); + #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS) + set_memory_r(0x00fcc000, 0x00fcffff, sound_bios); + unset_memory_w(0x00fcc000, 0x00fcffff); + #endif // } } else { unset_memory_rw(0xcc000, 0xcffff); + #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS) + unset_memory_rw(0x00fcc000, 0x00fcffff); + #endif } } @@ -701,12 +727,22 @@ void MEMBUS::update_sasi_bios() if(sasi_bios_selected) { if(sasi_bios_ram_selected) { set_memory_rw(0xd7000, 0xd7fff, sasi_bios_ram); + #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS) + set_memory_rw(0x00fd7000, 0x00fd7fff, sasi_bios_ram); + #endif } else { set_memory_r(0xd7000, 0xd7fff, sasi_bios); unset_memory_w(0xd7000, 0xd7fff); + #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS) + set_memory_r(0x00fd7000, 0x00fd7fff, sasi_bios); + unset_memory_w(0x00fd7000, 0x00fd7fff); + #endif } } else { unset_memory_rw(0xd7000, 0xd7fff); + #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS) + unset_memory_rw(0x00fd7000, 0x00fd7fff); + #endif } } #endif @@ -717,12 +753,22 @@ void MEMBUS::update_scsi_bios() if(scsi_bios_selected) { if(scsi_bios_ram_selected) { set_memory_rw(0xdc000, 0xdcfff, scsi_bios_ram); + #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS) + set_memory_rw(0x00fdc000, 0x00fdcfff, scsi_bios_ram); + #endif } else { set_memory_r(0xdc000, 0xdcfff, scsi_bios); unset_memory_w(0xdc000, 0xdcfff); + #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS) + set_memory_r(0x00fdc000, 0x00fdcfff, scsi_bios); + unset_memory_w(0x00fdc000, 0x00fdcfff); + #endif } } else { unset_memory_rw(0xdc000, 0xdcfff); + #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS) + unset_memory_rw(0x00fdc000, 0x00fdcfff); + #endif } } #endif @@ -736,9 +782,16 @@ void MEMBUS::update_ide_bios() // } else { set_memory_r(0xd8000, 0xdbfff, ide_bios); unset_memory_w(0xd8000, 0xdbfff); + #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS) + set_memory_r(0x00fd8000, 0x00fdbfff, ide_bios); + unset_memory_w(0x00fd8000, 0x00fdbfff); + #endif // } } else { unset_memory_rw(0xd8000, 0xdbfff); + #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS) + unset_memory_rw(0x00fd8000, 0x00fdbfff); + #endif } } #endif diff --git a/source/src/vm/pc9801/pc9801.cpp b/source/src/vm/pc9801/pc9801.cpp index 03ac5c94f..0d1150bd7 100644 --- a/source/src/vm/pc9801/pc9801.cpp +++ b/source/src/vm/pc9801/pc9801.cpp @@ -469,6 +469,7 @@ VM::VM(EMU* parent_emu) : VM_TEMPLATE(parent_emu) #if defined(SUPPORT_24BIT_ADDRESS) || defined(SUPPORT_32BIT_ADDRESS) cpureg->set_context_cpu(cpu); cpureg->set_context_membus(memory); + cpureg->set_context_piosys(pio_sys); #endif display->set_context_pic(pic); display->set_context_gdc_chr(gdc_chr, gdc_chr->get_ra()); @@ -620,6 +621,7 @@ VM::VM(EMU* parent_emu) : VM_TEMPLATE(parent_emu) #if defined(SUPPORT_24BIT_ADDRESS) || defined(SUPPORT_32BIT_ADDRESS) io->set_iomap_single_w(0x0029, dmareg); #endif + #if defined(SUPPORT_32BIT_ADDRESS) io->set_iomap_single_w(0x0e05, dmareg); io->set_iomap_single_w(0x0e07, dmareg); @@ -694,6 +696,7 @@ VM::VM(EMU* parent_emu) : VM_TEMPLATE(parent_emu) io->set_iomap_single_rw(0x0cc4, scsi); #endif #if defined(SUPPORT_IDE_IF) + //Q: MAME MAPPING has 0430h and 0432h as IDE control registers.20190408 K.O io->set_iomap_single_rw(0x0640, ide); io->set_iomap_single_rw(0x0642, ide); io->set_iomap_single_rw(0x0644, ide); @@ -726,7 +729,7 @@ VM::VM(EMU* parent_emu) : VM_TEMPLATE(parent_emu) io->set_iomap_single_rw(0xa5, display); io->set_iomap_single_rw(0xa9, display); #if defined(SUPPORT_EGC) - io->set_iomap_range_rw(0x04a0, 0x04af, display); + io->set_iomap_range_rw(0x04a0, 0x04af, display); // EGC REGS #endif io->set_iomap_alias_rw(0x0071, pit, 0); @@ -808,7 +811,7 @@ VM::VM(EMU* parent_emu) : VM_TEMPLATE(parent_emu) io->set_iomap_single_w(0x043d, memory); #endif #if !defined(SUPPORT_HIRESO) - io->set_iomap_single_w(0x043f, memory); + io->set_iomap_single_w(0x043f, memory); // ITF #endif #if defined(SUPPORT_24BIT_ADDRESS) || defined(SUPPORT_32BIT_ADDRESS) #if !defined(_PC98XA) @@ -846,6 +849,7 @@ VM::VM(EMU* parent_emu) : VM_TEMPLATE(parent_emu) io->set_iomap_alias_rw(0x0065, pio_mouse, 2); io->set_iomap_alias_rw(0x0067, pio_mouse, 3); #endif + // ToDo: MIDI@0xe0d0 - e0d3 #if defined(_PC98DO) || defined(_PC98DOPLUS) pc88event = new EVENT(this, emu); @@ -1687,7 +1691,7 @@ void VM::update_config() } } -#define STATE_VERSION 16 +#define STATE_VERSION 17 bool VM::process_state(FILEIO* state_fio, bool loading) { diff --git a/source/src/vm/pc9801/pc9801.h b/source/src/vm/pc9801/pc9801.h index e6a8eeaf4..c6150519a 100644 --- a/source/src/vm/pc9801/pc9801.h +++ b/source/src/vm/pc9801/pc9801.h @@ -208,8 +208,10 @@ // PC-9801-86 #define SUPPORT_PC98_OPNA #endif -#if defined(SUPPORT_24BIT_ADDRESS) || defined(SUPPORT_32BIT_ADDRESS) +#if defined(SUPPORT_24BIT_ADDRESS) #define MEMORY_ADDR_MAX 0x1000000 // 16MB +#elif defined(SUPPORT_32BIT_ADDRESS) + #define MEMORY_ADDR_MAX 0x10000000 // 256MB #else #define MEMORY_ADDR_MAX 0x100000 // 1MB #endif diff --git a/source/src/vm/pc9801/sasi_bios.cpp b/source/src/vm/pc9801/sasi_bios.cpp index c0c9d499c..5aa51a4a8 100644 --- a/source/src/vm/pc9801/sasi_bios.cpp +++ b/source/src/vm/pc9801/sasi_bios.cpp @@ -131,7 +131,7 @@ void BIOS::reset() return false; } - bool BIOS::bios_call_far_i86(uint32_t PC, uint16_t regs[], uint16_t sregs[], int32_t* ZeroFlag, int32_t* CarryFlag, int* cycles, uint64_t* total_cycles) +bool BIOS::bios_call_far_i86(uint32_t PC, uint16_t regs[], uint16_t sregs[], int32_t* ZeroFlag, int32_t* CarryFlag, int* cycles, uint64_t* total_cycles) { uint8_t *regs8 = (uint8_t *)regs; bool need_retcall = false; @@ -141,8 +141,8 @@ void BIOS::reset() // ToDo: Check ITF BANK for EPSON : // IF (ITF_ENABLED) && ((0xf8000 <= PC < 0x10000)) NOT CALL BIOS if(d_mem->is_sasi_bios_load()) return false; - // Check ADDRESS: This pseudo-bios acts only $fffc4 ($1B) : - if(PC != 0xfffc4) return false; // INT 1Bh + // Check ADDRESS: This pseudo-bios acts only $fffc4 ($1B) or $00ffffc4: + if((PC != 0xfffc4) && (PC != 0x00ffffc4)) return false; // INT 1Bh #if 1 static const int elapsed_cycle = 200; // From NP2 0.86+trunk/ OK? /* if((((AL & 0xf0) != 0x00) && ((AL & 0xf0) != 0x80))) */ { diff --git a/source/src/vm/upd7220.h b/source/src/vm/upd7220.h index 6e3bd20b3..79d5f7375 100644 --- a/source/src/vm/upd7220.h +++ b/source/src/vm/upd7220.h @@ -150,8 +150,6 @@ public: void event_callback(int event_id, int err); void update_timing(int new_clocks, double new_frames_per_sec, int new_lines_per_frame); - virtual void save_state(FILEIO* state_fio) {} - virtual bool load_state(FILEIO* state_fio) { return false; } // unique functions void set_context_drq(DEVICE* device, int id, uint32_t mask) -- 2.11.0