From 90e252f6f76fbf533176e34d906a1b6ee598733a Mon Sep 17 00:00:00 2001 From: Tobias Grosser Date: Wed, 20 Jul 2016 11:24:27 +0000 Subject: [PATCH] [InstCombine] Provide more test cases for cast-folding [NFC] Summary: In r275989 we enabled the folding of `logic(cast(icmp), cast(icmp))` to `cast(logic(icmp, icmp))`. Here we add more test cases to assure this folding works for all logical operations `and`/`or`/`xor`. Reviewers: grosser Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22561 Contributed-by: Matthias Reisinger git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276105 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/Transforms/InstCombine/zext.ll | 38 ++++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/test/Transforms/InstCombine/zext.ll b/test/Transforms/InstCombine/zext.ll index 47a82037276..db4dba98379 100644 --- a/test/Transforms/InstCombine/zext.ll +++ b/test/Transforms/InstCombine/zext.ll @@ -73,14 +73,14 @@ define <2 x i64> @fold_xor_zext_sandwich_vec(<2 x i1> %a) { ret <2 x i64> %zext2 } -; Assert that zexts in logic(zext(icmp), zext(icmp)) can be folded -; CHECK-LABEL: @fold_logic_zext_icmp( +; Assert that zexts in and(zext(icmp), zext(icmp)) can be folded +; CHECK-LABEL: @fold_and_zext_icmp( ; CHECK-NEXT: [[ICMP1:%.*]] = icmp sgt i64 %a, %b ; CHECK-NEXT: [[ICMP2:%.*]] = icmp slt i64 %a, %c ; CHECK-NEXT: [[AND:%.*]] = and i1 [[ICMP1]], [[ICMP2]] ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[AND]] to i8 ; CHECK-NEXT: ret i8 [[ZEXT]] -define i8 @fold_logic_zext_icmp(i64 %a, i64 %b, i64 %c) { +define i8 @fold_and_zext_icmp(i64 %a, i64 %b, i64 %c) { %1 = icmp sgt i64 %a, %b %2 = zext i1 %1 to i8 %3 = icmp slt i64 %a, %c @@ -89,6 +89,38 @@ define i8 @fold_logic_zext_icmp(i64 %a, i64 %b, i64 %c) { ret i8 %5 } +; Assert that zexts in or(zext(icmp), zext(icmp)) can be folded +; CHECK-LABEL: @fold_or_zext_icmp( +; CHECK-NEXT: [[ICMP1:%.*]] = icmp sgt i64 %a, %b +; CHECK-NEXT: [[ICMP2:%.*]] = icmp slt i64 %a, %c +; CHECK-NEXT: [[OR:%.*]] = or i1 [[ICMP1]], [[ICMP2]] +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[OR]] to i8 +; CHECK-NEXT: ret i8 [[ZEXT]] +define i8 @fold_or_zext_icmp(i64 %a, i64 %b, i64 %c) { + %1 = icmp sgt i64 %a, %b + %2 = zext i1 %1 to i8 + %3 = icmp slt i64 %a, %c + %4 = zext i1 %3 to i8 + %5 = or i8 %2, %4 + ret i8 %5 +} + +; Assert that zexts in xor(zext(icmp), zext(icmp)) can be folded +; CHECK-LABEL: @fold_xor_zext_icmp( +; CHECK-NEXT: [[ICMP1:%.*]] = icmp sgt i64 %a, %b +; CHECK-NEXT: [[ICMP2:%.*]] = icmp slt i64 %a, %c +; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[ICMP1]], [[ICMP2]] +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[XOR]] to i8 +; CHECK-NEXT: ret i8 [[ZEXT]] +define i8 @fold_xor_zext_icmp(i64 %a, i64 %b, i64 %c) { + %1 = icmp sgt i64 %a, %b + %2 = zext i1 %1 to i8 + %3 = icmp slt i64 %a, %c + %4 = zext i1 %3 to i8 + %5 = xor i8 %2, %4 + ret i8 %5 +} + ; Assert that zexts in logic(zext(icmp), zext(icmp)) are also folded accross ; nested logical operators. ; CHECK-LABEL: @fold_nested_logic_zext_icmp( -- 2.11.0