From 91d848ebf3bc7fd73fb1a4fc11bdb04225b3f37d Mon Sep 17 00:00:00 2001
From: bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Mon, 21 Jun 2004 22:46:48 +0000
Subject: [PATCH] disable PCI device for PMAC

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@966 c046a42c-6fe2-441c-8c8c-71466251a162
---
 hw/openpic.c  | 57 +++++++++++++++++++++++++++++++--------------------------
 hw/ppc_chrp.c |  4 +++-
 2 files changed, 34 insertions(+), 27 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index eab6d08114..d193cfe6f2 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -164,6 +164,7 @@ typedef struct IRQ_dst_t {
 
 struct openpic_t {
     PCIDevice pci_dev;
+    int mem_index;
     /* Global registers */
     uint32_t frep; /* Feature reporting register */
     uint32_t glbc; /* Global configuration register  */
@@ -937,7 +938,6 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
                         uint32_t addr, uint32_t size, int type)
 {
     openpic_t *opp;
-    int opp_io_memory;
 
     DPRINTF("Map OpenPIC\n");
     opp = (openpic_t *)pci_dev;
@@ -953,9 +953,7 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
     /* Per CPU registers */
     DPRINTF("Register OPENPIC dst   %08x => %08x\n",
             addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU);
-    opp_io_memory = cpu_register_io_memory(0, openpic_read,
-                                           openpic_write, opp);
-    cpu_register_physical_memory(addr, 0x40000, opp_io_memory);
+    cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
 #if 0 // Don't implement ISU for now
     opp_io_memory = cpu_register_io_memory(0, openpic_src_read,
                                            openpic_src_write);
@@ -964,8 +962,7 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
 #endif
 }
 
-openpic_t *openpic_init (PCIBus *bus,
-                         uint32_t isu_base, uint32_t idu_base, int nb_cpus)
+openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus)
 {
     openpic_t *opp;
     uint8_t *pci_conf;
@@ -974,25 +971,32 @@ openpic_t *openpic_init (PCIBus *bus,
     /* XXX: for now, only one CPU is supported */
     if (nb_cpus != 1)
         return NULL;
-    opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
-                                           -1, NULL, NULL);
-    if (opp == NULL)
-        return NULL;
-    pci_conf = opp->pci_dev.config;
-    pci_conf[0x00] = 0x14; // IBM MPIC2
-    pci_conf[0x01] = 0x10;
-    pci_conf[0x02] = 0xFF;
-    pci_conf[0x03] = 0xFF;
-    pci_conf[0x0a] = 0x80; // PIC
-    pci_conf[0x0b] = 0x08;
-    pci_conf[0x0e] = 0x00; // header_type
-    pci_conf[0x3d] = 0x00; // no interrupt pin
-
-    /* Register I/O spaces */
-    pci_register_io_region((PCIDevice *)opp, 0, 0x40000,
-                           PCI_ADDRESS_SPACE_MEM, &openpic_map);
-
-    isu_base &= 0xFFFC0000;
+    if (bus) {
+        opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
+                                               -1, NULL, NULL);
+        if (opp == NULL)
+            return NULL;
+        pci_conf = opp->pci_dev.config;
+        pci_conf[0x00] = 0x14; // IBM MPIC2
+        pci_conf[0x01] = 0x10;
+        pci_conf[0x02] = 0xFF;
+        pci_conf[0x03] = 0xFF;
+        pci_conf[0x0a] = 0x80; // PIC
+        pci_conf[0x0b] = 0x08;
+        pci_conf[0x0e] = 0x00; // header_type
+        pci_conf[0x3d] = 0x00; // no interrupt pin
+        
+        /* Register I/O spaces */
+        pci_register_io_region((PCIDevice *)opp, 0, 0x40000,
+                               PCI_ADDRESS_SPACE_MEM, &openpic_map);
+    } else {
+        opp = qemu_mallocz(sizeof(openpic_t));
+    }
+
+    opp->mem_index = cpu_register_io_memory(0, openpic_read,
+                                            openpic_write, opp);
+    
+    //    isu_base &= 0xFFFC0000;
     opp->nb_cpus = nb_cpus;
     /* Set IRQ types */
     for (i = 0; i < EXT_IRQ; i++) {
@@ -1013,6 +1017,7 @@ openpic_t *openpic_init (PCIBus *bus,
         opp->src[i].type = IRQ_INTERNAL;
     }
     openpic_reset(opp);
-
+    if (pmem_index)
+        *pmem_index = opp->mem_index;
     return opp;
 }
diff --git a/hw/ppc_chrp.c b/hw/ppc_chrp.c
index fce4348328..93835322fb 100644
--- a/hw/ppc_chrp.c
+++ b/hw/ppc_chrp.c
@@ -36,6 +36,7 @@ static int dbdma_mem_index;
 static int cuda_mem_index;
 static int ide0_mem_index;
 static int ide1_mem_index;
+static int openpic_mem_index;
 
 /* DBDMA: currently no op - should suffice right now */
 
@@ -87,6 +88,7 @@ static void macio_map(PCIDevice *pci_dev, int region_num,
     cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
     cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
     cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
+    cpu_register_physical_memory(addr + 0x40000, 0x40000, openpic_mem_index);
 }
 
 static void macio_init(PCIBus *bus)
@@ -191,7 +193,7 @@ void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
     /* init basic PC hardware */
     vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size, 
                    vga_ram_size);
-    openpic = openpic_init(pci_bus, 0x00000000, 0xF0000000, 1);
+    openpic = openpic_init(NULL, &openpic_mem_index, 1);
     pci_pmac_set_openpic(pci_bus, openpic);
     
     /* XXX: suppress that */
-- 
2.11.0