From 9325cc92eddcacd46e64b6190a7d0516d5627cef Mon Sep 17 00:00:00 2001
From: Hiroshi Inoue <inouehrs@jp.ibm.com>
Date: Tue, 31 Jul 2018 05:29:20 +0000
Subject: [PATCH] [InstSimplify] tests for D48828, D49981: fold extraction from
 std::pair

Minor touch up in the previous comment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338351 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/Transforms/InstSimplify/AndOrXor.ll | 14 +++++++-------
 test/Transforms/InstSimplify/shift.ll    | 10 +++++-----
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/test/Transforms/InstSimplify/AndOrXor.ll b/test/Transforms/InstSimplify/AndOrXor.ll
index b0fa1cfb8da..ed68f112127 100644
--- a/test/Transforms/InstSimplify/AndOrXor.ll
+++ b/test/Transforms/InstSimplify/AndOrXor.ll
@@ -999,8 +999,8 @@ define i64 @shl_or_and2(i32 %a, i1 %b) {
   ret i64 %tmp5
 }
 
-define i64 @shl_or_and3(i32 %a, i32 %b) {
 ; concatinate two 32-bit integers and extract lower 32-bit
+define i64 @shl_or_and3(i32 %a, i32 %b) {
 ; CHECK-LABEL: @shl_or_and3(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
@@ -1017,8 +1017,8 @@ define i64 @shl_or_and3(i32 %a, i32 %b) {
   ret i64 %tmp5
 }
 
-define i32 @shl_or_and4(i16 %a, i16 %b) {
 ; concatinate two 16-bit integers and extract higher 16-bit
+define i32 @shl_or_and4(i16 %a, i16 %b) {
 ; CHECK-LABEL: @shl_or_and4(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
@@ -1052,8 +1052,8 @@ define i128 @shl_or_and5(i64 %a, i1 %b) {
   ret i128 %tmp5
 }
 
+; A variation of above test cases; it fails due to the mask value
 define i32 @shl_or_and6(i16 %a, i16 %b) {
-; A variation of above test case, but fails due to the mask value
 ; CHECK-LABEL: @shl_or_and6(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
@@ -1070,8 +1070,8 @@ define i32 @shl_or_and6(i16 %a, i16 %b) {
   ret i32 %tmp5
 }
 
+; A variation of above test cases; it fails due to the mask value
 define i32 @shl_or_and7(i16 %a, i16 %b) {
-; A variation of above test case, but fails due to the mask value
 ; CHECK-LABEL: @shl_or_and7(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
@@ -1088,8 +1088,8 @@ define i32 @shl_or_and7(i16 %a, i16 %b) {
   ret i32 %tmp5
 }
 
+; A variation of above test cases; it fails due to the mask value
 define i32 @shl_or_and8(i16 %a, i16 %b) {
-; A variation of above test case, but fails due to the mask value
 ; CHECK-LABEL: @shl_or_and8(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
@@ -1111,14 +1111,14 @@ define <2 x i64> @shl_or_and1v(<2 x i32> %a, <2 x i1> %b) {
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
 ; CHECK-NEXT:    [[TMP2:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64>
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 32, i64 32>
-; CHECK-NEXT:    [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]]
+; CHECK-NEXT:    [[TMP4:%.*]] = or <2 x i64> [[TMP3]], [[TMP2]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = and <2 x i64> [[TMP4]], <i64 1, i64 1>
 ; CHECK-NEXT:    ret <2 x i64> [[TMP5]]
 ;
   %tmp1 = zext <2 x i32> %a to <2 x i64>
   %tmp2 = zext <2 x i1> %b to <2 x i64>
   %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32>
-  %tmp4 = or <2 x i64> %tmp2, %tmp3
+  %tmp4 = or <2 x i64> %tmp3, %tmp2
   %tmp5 = and <2 x i64> %tmp4, <i64 1, i64 1>
   ret <2 x i64> %tmp5
 }
diff --git a/test/Transforms/InstSimplify/shift.ll b/test/Transforms/InstSimplify/shift.ll
index 1978cfc1f3d..f49c76bf625 100644
--- a/test/Transforms/InstSimplify/shift.ll
+++ b/test/Transforms/InstSimplify/shift.ll
@@ -192,8 +192,8 @@ define i64 @shl_or_shr(i32 %a, i32 %b) {
   ret i64 %tmp5
 }
 
-define i64 @shl_or_shr2(i32 %a, i32 %b) {
 ; Since shift count of shl is smaller than the size of %b, OR cannot be eliminated.
+define i64 @shl_or_shr2(i32 %a, i32 %b) {
 ; CHECK-LABEL: @shl_or_shr2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
@@ -210,26 +210,26 @@ define i64 @shl_or_shr2(i32 %a, i32 %b) {
   ret i64 %tmp5
 }
 
-define <2 x i64> @shl_or_shr1v(<2 x i32> %a, <2 x i32> %b) {
 ; Unit test for vector integer
+define <2 x i64> @shl_or_shr1v(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: @shl_or_shr1v(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
 ; CHECK-NEXT:    [[TMP2:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i64>
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 32, i64 32>
-; CHECK-NEXT:    [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]]
+; CHECK-NEXT:    [[TMP4:%.*]] = or <2 x i64> [[TMP3]], [[TMP2]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = lshr <2 x i64> [[TMP4]], <i64 32, i64 32>
 ; CHECK-NEXT:    ret <2 x i64> [[TMP5]]
 ;
   %tmp1 = zext <2 x i32> %a to <2 x i64>
   %tmp2 = zext <2 x i32> %b to <2 x i64>
   %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32>
-  %tmp4 = or <2 x i64> %tmp2, %tmp3
+  %tmp4 = or <2 x i64> %tmp3, %tmp2
   %tmp5 = lshr <2 x i64> %tmp4, <i64 32, i64 32>
   ret <2 x i64> %tmp5
 }
 
-define <2 x i64> @shl_or_shr2v(<2 x i32> %a, <2 x i32> %b) {
 ; Negative unit test for vector integer
+define <2 x i64> @shl_or_shr2v(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: @shl_or_shr2v(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
 ; CHECK-NEXT:    [[TMP2:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i64>
-- 
2.11.0