From 94ca42ff0407d71bacc41de4032d8dbe6358d33d Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 7 Jul 2011 00:08:19 +0000 Subject: [PATCH] Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134569 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARM.td | 2 +- lib/Target/ARM/ARMSubtarget.cpp | 89 +++++-------------------- lib/Target/ARM/ARMSubtarget.h | 18 ++--- lib/Target/ARM/ARMTargetMachine.cpp | 9 ++- lib/Target/ARM/ARMTargetMachine.h | 3 +- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 46 +++++++++++++ lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h | 8 +++ 7 files changed, 84 insertions(+), 91 deletions(-) diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 39a3528836e..6d3a42fa400 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -27,7 +27,7 @@ def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3", "Enable VFP3 instructions">; def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON", "Enable NEON instructions">; -def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2", +def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", "Enable Thumb2 instructions">; def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", "Does not support ARM mode execution">; diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index a7010c5be1b..da572d2e5ee 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -37,7 +37,7 @@ StrictAlign("arm-strict-align", cl::Hidden, cl::desc("Disallow all unaligned memory accesses")); ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, bool isT) + const std::string &FS) : ARMGenSubtargetInfo() , ARMArchVersion(V4) , ARMProcFamily(Others) @@ -46,8 +46,8 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, , SlowFPVMLx(false) , HasVMLxForwarding(false) , SlowFPBrcc(false) - , IsThumb(isT) - , ThumbMode(Thumb1) + , IsThumb(false) + , HasThumb2(false) , NoARM(false) , PostRAScheduler(false) , IsR9Reserved(ReserveR9) @@ -68,65 +68,8 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, , TargetTriple(TT) , TargetABI(ARM_ABI_APCS) { // Determine default and user specified characteristics - - // When no arch is specified either by CPU or by attributes, make the default - // ARMv4T. - const char *ARMArchFeature = ""; if (CPUString.empty()) CPUString = "generic"; - if (CPUString == "generic" && (FS.empty() || FS == "generic")) { - ARMArchVersion = V4T; - ARMArchFeature = "+v4t"; - } - - // Set the boolean corresponding to the current target triple, or the default - // if one cannot be determined, to true. - unsigned Len = TT.length(); - unsigned Idx = 0; - - if (Len >= 5 && TT.substr(0, 4) == "armv") - Idx = 4; - else if (Len >= 6 && TT.substr(0, 5) == "thumb") { - IsThumb = true; - if (Len >= 7 && TT[5] == 'v') - Idx = 6; - } - if (Idx) { - unsigned SubVer = TT[Idx]; - if (SubVer >= '7' && SubVer <= '9') { - ARMArchVersion = V7A; - ARMArchFeature = "+v7a"; - if (Len >= Idx+2 && TT[Idx+1] == 'm') { - ARMArchVersion = V7M; - ARMArchFeature = "+v7m"; - } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { - ARMArchVersion = V7EM; - ARMArchFeature = "+v7em"; - } - } else if (SubVer == '6') { - ARMArchVersion = V6; - ARMArchFeature = "+v6"; - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { - ARMArchVersion = V6T2; - ARMArchFeature = "+v6t2"; - } - } else if (SubVer == '5') { - ARMArchVersion = V5T; - ARMArchFeature = "+v5t"; - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { - ARMArchVersion = V5TE; - ARMArchFeature = "+v5te"; - } - } else if (SubVer == '4') { - if (Len >= Idx+2 && TT[Idx+1] == 't') { - ARMArchVersion = V4T; - ARMArchFeature = "+v4t"; - } else { - ARMArchVersion = V4; - ARMArchFeature = ""; - } - } - } if (TT.find("eabi") != std::string::npos) TargetABI = ARM_ABI_AAPCS; @@ -134,12 +77,20 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, // Insert the architecture feature derived from the target triple into the // feature string. This is important for setting features that are implied // based on the architecture version. - std::string FSWithArch = std::string(ARMArchFeature); - if (FSWithArch.empty()) - FSWithArch = FS; - else if (!FS.empty()) - FSWithArch = FSWithArch + "," + FS; - ParseSubtargetFeatures(FSWithArch, CPUString); + std::string ArchFS = ARM_MC::ParseARMTriple(TT, IsThumb); + if (!FS.empty()) { + if (!ArchFS.empty()) + ArchFS = ArchFS + "," + FS; + else + ArchFS = FS; + } + + ParseSubtargetFeatures(ArchFS, CPUString); + + // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a + // ARM version or CPU and then remove this. + if (ARMArchVersion < V6T2 && hasThumb2()) + ARMArchVersion = V6T2; // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUString); @@ -147,12 +98,6 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, // After parsing Itineraries, set ItinData.IssueWidth. computeIssueWidth(); - // Thumb2 implies at least V6T2. - if (ARMArchVersion >= V6T2) - ThumbMode = Thumb2; - else if (ThumbMode >= Thumb2) - ARMArchVersion = V6T2; - if (isAAPCS_ABI()) stackAlignment = 8; diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index 66e4426091d..6969c38016b 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -14,6 +14,7 @@ #ifndef ARMSUBTARGET_H #define ARMSUBTARGET_H +#include "MCTargetDesc/ARMMCTargetDesc.h" #include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/ADT/Triple.h" @@ -39,11 +40,6 @@ protected: None, VFPv2, VFPv3, NEON }; - enum ThumbTypeEnum { - Thumb1, - Thumb2 - }; - /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE, /// V6, V6T2, V7A, V7M, V7EM. ARMArchEnum ARMArchVersion; @@ -73,8 +69,8 @@ protected: /// IsThumb - True if we are in thumb mode, false if in ARM mode. bool IsThumb; - /// ThumbMode - Indicates supported Thumb version. - ThumbTypeEnum ThumbMode; + /// HasThumb2 - True if Thumb2 instructions are supported. + bool HasThumb2; /// NoARM - True if subtarget does not support ARM mode execution. bool NoARM; @@ -161,7 +157,7 @@ protected: /// of the specified triple. /// ARMSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, bool isThumb); + const std::string &FS); /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size /// that still makes it profitable to inline the call. @@ -217,9 +213,9 @@ protected: bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } bool isThumb() const { return IsThumb; } - bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); } - bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } - bool hasThumb2() const { return ThumbMode >= Thumb2; } + bool isThumb1Only() const { return IsThumb && !HasThumb2; } + bool isThumb2() const { return IsThumb && HasThumb2; } + bool hasThumb2() const { return HasThumb2; } bool isR9Reserved() const { return IsR9Reserved; } diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 80e7d559470..bb3184ee73b 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -79,10 +79,9 @@ extern "C" void LLVMInitializeARMTarget() { ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, - const std::string &FS, - bool isThumb) + const std::string &FS) : LLVMTargetMachine(T, TT), - Subtarget(TT, CPU, FS, isThumb), + Subtarget(TT, CPU, FS), JITInfo(), InstrItins(Subtarget.getInstrItineraryData()) { DefRelocModel = getRelocationModel(); @@ -95,7 +94,7 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : ARMBaseTargetMachine(T, TT, CPU, FS, false), InstrInfo(Subtarget), + : ARMBaseTargetMachine(T, TT, CPU, FS), InstrInfo(Subtarget), DataLayout(Subtarget.isAPCS_ABI() ? std::string("e-p:32:32-f64:32:64-i64:32:64-" "v128:32:128-v64:32:64-n32") : @@ -113,7 +112,7 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : ARMBaseTargetMachine(T, TT, CPU, FS, true), + : ARMBaseTargetMachine(T, TT, CPU, FS), InstrInfo(Subtarget.hasThumb2() ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index a4a792763d0..bc3d46a50ea 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -41,8 +41,7 @@ private: public: ARMBaseTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, - bool isThumb); + const std::string &CPU, const std::string &FS); virtual ARMJITInfo *getJITInfo() { return &JITInfo; } virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 198c25d863d..f2b6d252245 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -72,3 +72,49 @@ extern "C" void LLVMInitializeARMMCSubtargetInfo() { TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, createARMMCSubtargetInfo); } + +std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) { + // Set the boolean corresponding to the current target triple, or the default + // if one cannot be determined, to true. + unsigned Len = TT.size(); + unsigned Idx = 0; + + if (Len >= 5 && TT.substr(0, 4) == "armv") + Idx = 4; + else if (Len >= 6 && TT.substr(0, 5) == "thumb") { + IsThumb = true; + if (Len >= 7 && TT[5] == 'v') + Idx = 6; + } + + std::string ARMArchFeature; + if (Idx) { + unsigned SubVer = TT[Idx]; + if (SubVer >= '7' && SubVer <= '9') { + ARMArchFeature = "+v7a"; + if (Len >= Idx+2 && TT[Idx+1] == 'm') { + ARMArchFeature = "+v7m"; + } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { + ARMArchFeature = "+v7em"; + } + } else if (SubVer == '6') { + ARMArchFeature = "+v6"; + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { + ARMArchFeature = "+v6t2"; + } + } else if (SubVer == '5') { + ARMArchFeature = "+v5t"; + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { + ARMArchFeature = "+v5te"; + } + } else if (SubVer == '4') { + if (Len >= Idx+2 && TT[Idx+1] == 't') { + ARMArchFeature = "+v4t"; + } else { + ARMArchFeature = ""; + } + } + } + + return ARMArchFeature; +} diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h index a486cffcfd0..0c2378409f4 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h @@ -14,10 +14,18 @@ #ifndef ARMMCTARGETDESC_H #define ARMMCTARGETDESC_H +#include + namespace llvm { class Target; +class StringRef; extern Target TheARMTarget, TheThumbTarget; + +namespace ARM_MC { + std::string ParseARMTriple(StringRef TT, bool &IsThumb); +} + } // End llvm namespace // Defines symbolic names for ARM registers. This defines a mapping from -- 2.11.0