From 9555021cfc6c57d050107e45d0dc27b753ac6c13 Mon Sep 17 00:00:00 2001
From: astoria-d <astoria-d@mail.goo.ne.jp>
Date: Sun, 11 Aug 2013 17:46:32 +0900
Subject: [PATCH] - dec zp,x/abs,x - inc zp,x/abs,x supported.

---
 simulation/cpu/decoder.vhd   | 16 ++++++++++++++++
 tools/test-image/sample1.asm | 25 +++++++++++++++++++++++++
 2 files changed, 41 insertions(+)

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index e5ba309..1744fc7 100644
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -1881,6 +1881,10 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#d6#, dsize) then
                     --zp, x
                     d_print("dec");
+                    a4_zp_x;
+                    if exec_cycle = T5 then
+                        set_nz_from_bus;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#ce#, dsize) then
                     --abs
@@ -1893,6 +1897,10 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#de#, dsize) then
                     --abs, x
                     d_print("dec");
+                    a4_abs_x;
+                    if exec_cycle = T6 then
+                        set_nz_from_bus;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#e6#, dsize) then
                     --zp
@@ -1905,6 +1913,10 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#f6#, dsize) then
                     --zp, x
                     d_print("inc");
+                    a4_zp_x;
+                    if exec_cycle = T5 then
+                        set_nz_from_bus;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#ee#, dsize) then
                     --abs
@@ -1917,6 +1929,10 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#fe#, dsize) then
                     --abs, x
                     d_print("inc");
+                    a4_abs_x;
+                    if exec_cycle = T6 then
+                        set_nz_from_bus;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#46#, dsize) then
                     --zp
diff --git a/tools/test-image/sample1.asm b/tools/test-image/sample1.asm
index 5036571..4e001cb 100644
--- a/tools/test-image/sample1.asm
+++ b/tools/test-image/sample1.asm
@@ -551,6 +551,31 @@ boundary_3_4:
     ldx #$55
     ldx $d0, y
 
+    ;;dec zp, x/abs, x
+    ;;inc zp, x/abs, x
+    lda #$00
+    ldx #$e4
+    sta $88
+    ldy #$00
+    dec $a4, x
+
+    ldx #$64
+    stx $0722
+    dec $06be, x
+
+    lda #$fe
+    ldx #$e4
+    sta $88
+    inc $a4, x
+    inc $a4, x
+    inc $a4, x
+
+    ldx #$64
+    stx $0722
+    inc $06be, x
+
+
+    ;;done...
     ;;infinite loop.
 mainloop:
 	jmp	mainloop
-- 
2.11.0