From 9585879d46fe412cbcfd50510e59e8ffe85b055f Mon Sep 17 00:00:00 2001 From: Neil Roberts Date: Mon, 11 May 2015 14:00:42 +0100 Subject: [PATCH] i956: Add a function to load a 64-bit register from a buffer Adds brw_load_register_mem64 which is similar to brw_load_register_mem except that it queues two GEN7_MI_LOAD_REGISTER_MEM commands in order to load both halves of a 64-bit register. The function is implemented by splitting the 32-bit version into an internal helper function which takes a size. This will later be used to set the 64-bit predicate source registers. Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.h | 5 +++ src/mesa/drivers/dri/i965/intel_batchbuffer.c | 55 ++++++++++++++++++++------- 2 files changed, 46 insertions(+), 14 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 834aaa45737..c794fa43973 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1606,6 +1606,11 @@ void brw_load_register_mem(struct brw_context *brw, drm_intel_bo *bo, uint32_t read_domains, uint32_t write_domain, uint32_t offset); +void brw_load_register_mem64(struct brw_context *brw, + uint32_t reg, + drm_intel_bo *bo, + uint32_t read_domains, uint32_t write_domain, + uint32_t offset); /*====================================================================== * brw_state_dump.c diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index e522e4e9c1d..ed659ed625e 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -743,27 +743,54 @@ intel_batchbuffer_emit_mi_flush(struct brw_context *brw) brw_render_cache_set_clear(brw); } -void -brw_load_register_mem(struct brw_context *brw, - uint32_t reg, - drm_intel_bo *bo, - uint32_t read_domains, uint32_t write_domain, - uint32_t offset) +static void +load_sized_register_mem(struct brw_context *brw, + uint32_t reg, + drm_intel_bo *bo, + uint32_t read_domains, uint32_t write_domain, + uint32_t offset, + int size) { + int i; + /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */ assert(brw->gen >= 7); if (brw->gen >= 8) { - BEGIN_BATCH(4); - OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2)); - OUT_BATCH(reg); - OUT_RELOC64(bo, read_domains, write_domain, offset); + BEGIN_BATCH(4 * size); + for (i = 0; i < size; i++) { + OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2)); + OUT_BATCH(reg + i * 4); + OUT_RELOC64(bo, read_domains, write_domain, offset + i * 4); + } ADVANCE_BATCH(); } else { - BEGIN_BATCH(3); - OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2)); - OUT_BATCH(reg); - OUT_RELOC(bo, read_domains, write_domain, offset); + BEGIN_BATCH(3 * size); + for (i = 0; i < size; i++) { + OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2)); + OUT_BATCH(reg + i * 4); + OUT_RELOC(bo, read_domains, write_domain, offset + i * 4); + } ADVANCE_BATCH(); } } + +void +brw_load_register_mem(struct brw_context *brw, + uint32_t reg, + drm_intel_bo *bo, + uint32_t read_domains, uint32_t write_domain, + uint32_t offset) +{ + load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 1); +} + +void +brw_load_register_mem64(struct brw_context *brw, + uint32_t reg, + drm_intel_bo *bo, + uint32_t read_domains, uint32_t write_domain, + uint32_t offset) +{ + load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 2); +} -- 2.11.0