From 95aa4b0a44a4a0789c43fd2c4b9d0ee94fd9b0ec Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 20 Mar 2018 03:55:17 +0000 Subject: [PATCH] [X86] Fix the SchedRW for memory forms of CMP and TEST. They were incorrectly marked as RMW operations. Some of the CMP instrucions worked, but the ones that use a similar encoding as RMW form of ADD ended up marked as RMW. TEST used the same tablegen class as some of the CMPs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327947 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrArithmetic.td | 39 +++++++++--------- test/CodeGen/X86/schedule-x86_64.ll | 76 ++++++++++++++++++------------------ 2 files changed, 59 insertions(+), 56 deletions(-) diff --git a/lib/Target/X86/X86InstrArithmetic.td b/lib/Target/X86/X86InstrArithmetic.td index 331168cbc60..edb419861c8 100644 --- a/lib/Target/X86/X86InstrArithmetic.td +++ b/lib/Target/X86/X86InstrArithmetic.td @@ -828,30 +828,31 @@ class BinOpMR opcode, string mnemonic, X86TypeInfo typeinfo, list pattern, InstrItinClass itin = IIC_BIN_MEM> : ITy, - Sched<[WriteALULd, WriteRMW]>; + mnemonic, "{$src, $dst|$dst, $src}", pattern, itin>; // BinOpMR_RMW - Instructions like "add [mem], reg". class BinOpMR_RMW opcode, string mnemonic, X86TypeInfo typeinfo, SDNode opnode> : BinOpMR; + (implicit EFLAGS)]>, Sched<[WriteALULd, WriteRMW]>; // BinOpMR_RMW_FF - Instructions like "adc [mem], reg". class BinOpMR_RMW_FF opcode, string mnemonic, X86TypeInfo typeinfo, SDNode opnode> : BinOpMR; + [(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS), + addr:$dst), + (implicit EFLAGS)], IIC_BIN_CARRY_MEM>, + Sched<[WriteALULd, WriteRMW]>; // BinOpMR_F - Instructions like "cmp [mem], reg". class BinOpMR_F opcode, string mnemonic, X86TypeInfo typeinfo, SDPatternOperator opnode> : BinOpMR; + typeinfo.RegClass:$src))]>, + Sched<[WriteALULd, ReadAfterLd]>; // BinOpMI - Instructions like "add [mem], imm". class BinOpMI opcode, string mnemonic, X86TypeInfo typeinfo, @@ -859,8 +860,7 @@ class BinOpMI opcode, string mnemonic, X86TypeInfo typeinfo, InstrItinClass itin = IIC_BIN_MEM> : ITy, - Sched<[WriteALULd, WriteRMW]> { + mnemonic, "{$src, $dst|$dst, $src}", pattern, itin> { let ImmT = typeinfo.ImmEncoding; } @@ -870,21 +870,23 @@ class BinOpMI_RMW opcode, string mnemonic, X86TypeInfo typeinfo, : BinOpMI; + (implicit EFLAGS)]>, Sched<[WriteALULd, WriteRMW]>; // BinOpMI_RMW_FF - Instructions like "adc [mem], imm". class BinOpMI_RMW_FF opcode, string mnemonic, X86TypeInfo typeinfo, SDNode opnode, Format f> : BinOpMI; + typeinfo.ImmOperator:$src, EFLAGS), addr:$dst), + (implicit EFLAGS)], IIC_BIN_CARRY_MEM>, + Sched<[WriteALULd, WriteRMW]>; // BinOpMI_F - Instructions like "cmp [mem], imm". class BinOpMI_F opcode, string mnemonic, X86TypeInfo typeinfo, SDPatternOperator opnode, Format f> : BinOpMI; + typeinfo.ImmOperator:$src))]>, + Sched<[WriteALULd, ReadAfterLd]>; // BinOpMI8 - Instructions like "add [mem], imm8". class BinOpMI8 : ITy<0x82, f, typeinfo, (outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src), - mnemonic, "{$src, $dst|$dst, $src}", pattern, itin>, - Sched<[WriteALULd, WriteRMW]> { + mnemonic, "{$src, $dst|$dst, $src}", pattern, itin> { let ImmT = Imm8; // Always 8-bit immediate. } @@ -903,7 +904,7 @@ class BinOpMI8_RMW; + (implicit EFLAGS)]>, Sched<[WriteALULd, WriteRMW]>; // BinOpMI8_RMW_FF - Instructions like "adc [mem], imm8". class BinOpMI8_RMW_FF; + (implicit EFLAGS)], IIC_BIN_CARRY_MEM>, + Sched<[WriteALULd, WriteRMW]>; // BinOpMI8_F - Instructions like "cmp [mem], imm8". class BinOpMI8_F : BinOpMI8; + typeinfo.Imm8Operator:$src))]>, + Sched<[WriteALULd, ReadAfterLd]>; // BinOpAI - Instructions like "add %eax, %eax, imm", that imp-def EFLAGS. class BinOpAI opcode, string mnemonic, X86TypeInfo typeinfo, diff --git a/test/CodeGen/X86/schedule-x86_64.ll b/test/CodeGen/X86/schedule-x86_64.ll index e2c74715349..77f047a00a3 100644 --- a/test/CodeGen/X86/schedule-x86_64.ll +++ b/test/CodeGen/X86/schedule-x86_64.ll @@ -3585,9 +3585,9 @@ define void @test_cmp_8(i8 %a0, i8* %a1) optsize { ; SLM-NEXT: #APP ; SLM-NEXT: cmpb $7, %al # sched: [1:0.50] ; SLM-NEXT: cmpb $7, %dil # sched: [1:0.50] -; SLM-NEXT: cmpb $7, (%rsi) # sched: [4:2.00] +; SLM-NEXT: cmpb $7, (%rsi) # sched: [4:1.00] ; SLM-NEXT: cmpb %dil, %dil # sched: [1:0.50] -; SLM-NEXT: cmpb %dil, (%rsi) # sched: [4:2.00] +; SLM-NEXT: cmpb %dil, (%rsi) # sched: [4:1.00] ; SLM-NEXT: cmpb (%rsi), %dil # sched: [4:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retq # sched: [4:1.00] @@ -3669,9 +3669,9 @@ define void @test_cmp_8(i8 %a0, i8* %a1) optsize { ; ZNVER1-NEXT: #APP ; ZNVER1-NEXT: cmpb $7, %al # sched: [1:0.25] ; ZNVER1-NEXT: cmpb $7, %dil # sched: [1:0.25] -; ZNVER1-NEXT: cmpb $7, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: cmpb $7, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: cmpb %dil, %dil # sched: [1:0.25] -; ZNVER1-NEXT: cmpb %dil, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: cmpb %dil, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: cmpb (%rsi), %dil # sched: [5:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retq # sched: [1:0.50] @@ -3721,11 +3721,11 @@ define void @test_cmp_16(i16 %a0, i16* %a1) optsize { ; SLM-NEXT: cmpw $511, %di # imm = 0x1FF ; SLM-NEXT: # sched: [1:0.50] ; SLM-NEXT: cmpw $511, (%rsi) # imm = 0x1FF -; SLM-NEXT: # sched: [4:2.00] +; SLM-NEXT: # sched: [4:1.00] ; SLM-NEXT: cmpw $7, %di # sched: [1:0.50] -; SLM-NEXT: cmpw $7, (%rsi) # sched: [4:2.00] +; SLM-NEXT: cmpw $7, (%rsi) # sched: [4:1.00] ; SLM-NEXT: cmpw %di, %di # sched: [1:0.50] -; SLM-NEXT: cmpw %di, (%rsi) # sched: [4:2.00] +; SLM-NEXT: cmpw %di, (%rsi) # sched: [4:1.00] ; SLM-NEXT: cmpw (%rsi), %di # sched: [4:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retq # sched: [4:1.00] @@ -3840,11 +3840,11 @@ define void @test_cmp_16(i16 %a0, i16* %a1) optsize { ; ZNVER1-NEXT: cmpw $511, %di # imm = 0x1FF ; ZNVER1-NEXT: # sched: [1:0.25] ; ZNVER1-NEXT: cmpw $511, (%rsi) # imm = 0x1FF -; ZNVER1-NEXT: # sched: [5:1.00] +; ZNVER1-NEXT: # sched: [5:0.50] ; ZNVER1-NEXT: cmpw $7, %di # sched: [1:0.25] -; ZNVER1-NEXT: cmpw $7, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: cmpw $7, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: cmpw %di, %di # sched: [1:0.25] -; ZNVER1-NEXT: cmpw %di, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: cmpw %di, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: cmpw (%rsi), %di # sched: [5:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retq # sched: [1:0.50] @@ -3894,11 +3894,11 @@ define void @test_cmp_32(i32 %a0, i32* %a1) optsize { ; SLM-NEXT: cmpl $665536, %edi # imm = 0xA27C0 ; SLM-NEXT: # sched: [1:0.50] ; SLM-NEXT: cmpl $665536, (%rsi) # imm = 0xA27C0 -; SLM-NEXT: # sched: [4:2.00] +; SLM-NEXT: # sched: [4:1.00] ; SLM-NEXT: cmpl $7, %edi # sched: [1:0.50] -; SLM-NEXT: cmpl $7, (%rsi) # sched: [4:2.00] +; SLM-NEXT: cmpl $7, (%rsi) # sched: [4:1.00] ; SLM-NEXT: cmpl %edi, %edi # sched: [1:0.50] -; SLM-NEXT: cmpl %edi, (%rsi) # sched: [4:2.00] +; SLM-NEXT: cmpl %edi, (%rsi) # sched: [4:1.00] ; SLM-NEXT: cmpl (%rsi), %edi # sched: [4:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retq # sched: [4:1.00] @@ -4013,11 +4013,11 @@ define void @test_cmp_32(i32 %a0, i32* %a1) optsize { ; ZNVER1-NEXT: cmpl $665536, %edi # imm = 0xA27C0 ; ZNVER1-NEXT: # sched: [1:0.25] ; ZNVER1-NEXT: cmpl $665536, (%rsi) # imm = 0xA27C0 -; ZNVER1-NEXT: # sched: [5:1.00] +; ZNVER1-NEXT: # sched: [5:0.50] ; ZNVER1-NEXT: cmpl $7, %edi # sched: [1:0.25] -; ZNVER1-NEXT: cmpl $7, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: cmpl $7, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: cmpl %edi, %edi # sched: [1:0.25] -; ZNVER1-NEXT: cmpl %edi, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: cmpl %edi, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: cmpl (%rsi), %edi # sched: [5:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retq # sched: [1:0.50] @@ -4067,11 +4067,11 @@ define void @test_cmp_64(i64 %a0, i64* %a1) optsize { ; SLM-NEXT: cmpq $665536, %rdi # imm = 0xA27C0 ; SLM-NEXT: # sched: [1:0.50] ; SLM-NEXT: cmpq $665536, (%rsi) # imm = 0xA27C0 -; SLM-NEXT: # sched: [4:2.00] +; SLM-NEXT: # sched: [4:1.00] ; SLM-NEXT: cmpq $7, %rdi # sched: [1:0.50] -; SLM-NEXT: cmpq $7, (%rsi) # sched: [4:2.00] +; SLM-NEXT: cmpq $7, (%rsi) # sched: [4:1.00] ; SLM-NEXT: cmpq %rdi, %rdi # sched: [1:0.50] -; SLM-NEXT: cmpq %rdi, (%rsi) # sched: [4:2.00] +; SLM-NEXT: cmpq %rdi, (%rsi) # sched: [4:1.00] ; SLM-NEXT: cmpq (%rsi), %rdi # sched: [4:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retq # sched: [4:1.00] @@ -4186,11 +4186,11 @@ define void @test_cmp_64(i64 %a0, i64* %a1) optsize { ; ZNVER1-NEXT: cmpq $665536, %rdi # imm = 0xA27C0 ; ZNVER1-NEXT: # sched: [1:0.25] ; ZNVER1-NEXT: cmpq $665536, (%rsi) # imm = 0xA27C0 -; ZNVER1-NEXT: # sched: [5:1.00] +; ZNVER1-NEXT: # sched: [5:0.50] ; ZNVER1-NEXT: cmpq $7, %rdi # sched: [1:0.25] -; ZNVER1-NEXT: cmpq $7, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: cmpq $7, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: cmpq %rdi, %rdi # sched: [1:0.25] -; ZNVER1-NEXT: cmpq %rdi, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: cmpq %rdi, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: cmpq (%rsi), %rdi # sched: [5:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retq # sched: [1:0.50] @@ -15193,9 +15193,9 @@ define void @test_test_8(i8 %a0, i8* %a1) optsize { ; SLM-NEXT: #APP ; SLM-NEXT: testb $7, %al # sched: [1:0.50] ; SLM-NEXT: testb $7, %dil # sched: [1:0.50] -; SLM-NEXT: testb $7, (%rsi) # sched: [4:2.00] +; SLM-NEXT: testb $7, (%rsi) # sched: [4:1.00] ; SLM-NEXT: testb %dil, %dil # sched: [1:0.50] -; SLM-NEXT: testb %dil, (%rsi) # sched: [4:2.00] +; SLM-NEXT: testb %dil, (%rsi) # sched: [4:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retq # sched: [4:1.00] ; @@ -15270,9 +15270,9 @@ define void @test_test_8(i8 %a0, i8* %a1) optsize { ; ZNVER1-NEXT: #APP ; ZNVER1-NEXT: testb $7, %al # sched: [1:0.25] ; ZNVER1-NEXT: testb $7, %dil # sched: [1:0.25] -; ZNVER1-NEXT: testb $7, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: testb $7, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: testb %dil, %dil # sched: [1:0.25] -; ZNVER1-NEXT: testb %dil, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: testb %dil, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retq # sched: [1:0.50] tail call void asm "testb $2, %AL \0A\09 testb $2, $0 \0A\09 testb $2, $1 \0A\09 testb $0, $0 \0A\09 testb $0, $1", "r,*m,i"(i8 %a0, i8* %a1, i8 7) nounwind @@ -15315,9 +15315,9 @@ define void @test_test_16(i16 %a0, i16* %a1) optsize { ; SLM-NEXT: testw $511, %di # imm = 0x1FF ; SLM-NEXT: # sched: [1:0.50] ; SLM-NEXT: testw $511, (%rsi) # imm = 0x1FF -; SLM-NEXT: # sched: [4:2.00] +; SLM-NEXT: # sched: [4:1.00] ; SLM-NEXT: testw %di, %di # sched: [1:0.50] -; SLM-NEXT: testw %di, (%rsi) # sched: [4:2.00] +; SLM-NEXT: testw %di, (%rsi) # sched: [4:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retq # sched: [4:1.00] ; @@ -15413,9 +15413,9 @@ define void @test_test_16(i16 %a0, i16* %a1) optsize { ; ZNVER1-NEXT: testw $511, %di # imm = 0x1FF ; ZNVER1-NEXT: # sched: [1:0.25] ; ZNVER1-NEXT: testw $511, (%rsi) # imm = 0x1FF -; ZNVER1-NEXT: # sched: [5:1.00] +; ZNVER1-NEXT: # sched: [5:0.50] ; ZNVER1-NEXT: testw %di, %di # sched: [1:0.25] -; ZNVER1-NEXT: testw %di, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: testw %di, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retq # sched: [1:0.50] tail call void asm "testw $2, %AX \0A\09 testw $2, $0 \0A\09 testw $2, $1 \0A\09 testw $0, $0 \0A\09 testw $0, $1", "r,*m,i"(i16 %a0, i16* %a1, i16 511) nounwind @@ -15458,9 +15458,9 @@ define void @test_test_32(i32 %a0, i32* %a1) optsize { ; SLM-NEXT: testl $665536, %edi # imm = 0xA27C0 ; SLM-NEXT: # sched: [1:0.50] ; SLM-NEXT: testl $665536, (%rsi) # imm = 0xA27C0 -; SLM-NEXT: # sched: [4:2.00] +; SLM-NEXT: # sched: [4:1.00] ; SLM-NEXT: testl %edi, %edi # sched: [1:0.50] -; SLM-NEXT: testl %edi, (%rsi) # sched: [4:2.00] +; SLM-NEXT: testl %edi, (%rsi) # sched: [4:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retq # sched: [4:1.00] ; @@ -15556,9 +15556,9 @@ define void @test_test_32(i32 %a0, i32* %a1) optsize { ; ZNVER1-NEXT: testl $665536, %edi # imm = 0xA27C0 ; ZNVER1-NEXT: # sched: [1:0.25] ; ZNVER1-NEXT: testl $665536, (%rsi) # imm = 0xA27C0 -; ZNVER1-NEXT: # sched: [5:1.00] +; ZNVER1-NEXT: # sched: [5:0.50] ; ZNVER1-NEXT: testl %edi, %edi # sched: [1:0.25] -; ZNVER1-NEXT: testl %edi, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: testl %edi, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retq # sched: [1:0.50] tail call void asm "testl $2, %EAX \0A\09 testl $2, $0 \0A\09 testl $2, $1 \0A\09 testl $0, $0 \0A\09 testl $0, $1", "r,*m,i"(i32 %a0, i32* %a1, i32 665536) nounwind @@ -15601,9 +15601,9 @@ define void @test_test_64(i64 %a0, i64* %a1) optsize { ; SLM-NEXT: testq $665536, %rdi # imm = 0xA27C0 ; SLM-NEXT: # sched: [1:0.50] ; SLM-NEXT: testq $665536, (%rsi) # imm = 0xA27C0 -; SLM-NEXT: # sched: [4:2.00] +; SLM-NEXT: # sched: [4:1.00] ; SLM-NEXT: testq %rdi, %rdi # sched: [1:0.50] -; SLM-NEXT: testq %rdi, (%rsi) # sched: [4:2.00] +; SLM-NEXT: testq %rdi, (%rsi) # sched: [4:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: retq # sched: [4:1.00] ; @@ -15699,9 +15699,9 @@ define void @test_test_64(i64 %a0, i64* %a1) optsize { ; ZNVER1-NEXT: testq $665536, %rdi # imm = 0xA27C0 ; ZNVER1-NEXT: # sched: [1:0.25] ; ZNVER1-NEXT: testq $665536, (%rsi) # imm = 0xA27C0 -; ZNVER1-NEXT: # sched: [5:1.00] +; ZNVER1-NEXT: # sched: [5:0.50] ; ZNVER1-NEXT: testq %rdi, %rdi # sched: [1:0.25] -; ZNVER1-NEXT: testq %rdi, (%rsi) # sched: [5:1.00] +; ZNVER1-NEXT: testq %rdi, (%rsi) # sched: [5:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retq # sched: [1:0.50] tail call void asm "testq $2, %RAX \0A\09 testq $2, $0 \0A\09 testq $2, $1 \0A\09 testq $0, $0 \0A\09 testq $0, $1", "r,*m,i"(i64 %a0, i64* %a1, i32 665536) nounwind -- 2.11.0