From 969473a9e08bfdc2138d21dd36b2594171c3aae0 Mon Sep 17 00:00:00 2001 From: Hardik Kantilal Patel Date: Wed, 8 Feb 2017 16:54:43 +0530 Subject: [PATCH] icnss: Avoid DOMAIN_ATTR_ATOMIC setting during S1 bypass While initializing the SMMU with DOMAIN_ATTR_ATOMIC attribute iommu driver always vote for aggre2_noc_clk during suspend mode which result into power penalty. To resolve this issue avoid configuring DOMAIN_ATTR_ATOMIC attribute in S1_BYPASS mode. CRs-fixed: 2004562 Change-Id: Ic5d4b2864f58098fd29da48e5f977434e356b1e0 Signed-off-by: Hardik Kantilal Patel --- Documentation/devicetree/bindings/cnss/icnss.txt | 2 ++ drivers/soc/qcom/icnss.c | 22 +++++++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/cnss/icnss.txt b/Documentation/devicetree/bindings/cnss/icnss.txt index 15feda3b7407..a1cbf480890a 100644 --- a/Documentation/devicetree/bindings/cnss/icnss.txt +++ b/Documentation/devicetree/bindings/cnss/icnss.txt @@ -19,6 +19,7 @@ Required properties: Optional properties: - qcom,icnss-vadc: VADC handle for vph_pwr read APIs. - qcom,icnss-adc_tm: VADC handle for vph_pwr notification APIs. + - qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass Example: @@ -43,4 +44,5 @@ Example: <0 140 0 /* CE10 */ >, <0 141 0 /* CE11 */ >; qcom,wlan-msa-memory = <0x200000>; + qcom,smmu-s1-bypass; }; diff --git a/drivers/soc/qcom/icnss.c b/drivers/soc/qcom/icnss.c index 7c08c28aeda8..4f0672513b87 100644 --- a/drivers/soc/qcom/icnss.c +++ b/drivers/soc/qcom/icnss.c @@ -334,6 +334,7 @@ static struct icnss_priv { struct ramdump_device *msa0_dump_dev; bool is_wlan_mac_set; struct icnss_wlan_mac_addr wlan_mac_addr; + bool bypass_s1_smmu; } *penv; static void icnss_pm_stay_awake(struct icnss_priv *priv) @@ -2914,13 +2915,15 @@ static int icnss_smmu_init(struct icnss_priv *priv) goto map_fail; } - ret = iommu_domain_set_attr(mapping->domain, - DOMAIN_ATTR_ATOMIC, - &atomic_ctx); - if (ret < 0) { - icnss_pr_err("Set atomic_ctx attribute failed, err = %d\n", - ret); - goto set_attr_fail; + if (!priv->bypass_s1_smmu) { + ret = iommu_domain_set_attr(mapping->domain, + DOMAIN_ATTR_ATOMIC, + &atomic_ctx); + if (ret < 0) { + icnss_pr_err("Set atomic_ctx attribute failed, err = %d\n", + ret); + goto set_attr_fail; + } } ret = iommu_domain_set_attr(mapping->domain, @@ -3666,6 +3669,11 @@ static int icnss_probe(struct platform_device *pdev) if (ret == -EPROBE_DEFER) goto out; + if (of_property_read_bool(pdev->dev.of_node, "qcom,smmu-s1-bypass")) + priv->bypass_s1_smmu = true; + + icnss_pr_dbg("SMMU S1 BYPASS = %d\n", priv->bypass_s1_smmu); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase"); if (!res) { icnss_pr_err("Memory base not found in DT\n"); -- 2.11.0