From 96d0a4da9fc2e616d4bf29b7878def683b9e47ae Mon Sep 17 00:00:00 2001
From: Diana Picus <diana.picus@linaro.org>
Date: Wed, 10 Jan 2018 11:13:31 +0000
Subject: [PATCH] [ARM GlobalISel] Map G_FNEG to the FPR bank

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322169 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMRegisterBankInfo.cpp            |  3 +-
 test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 49 +++++++++++++++++++++++
 2 files changed, 51 insertions(+), 1 deletion(-)

diff --git a/lib/Target/ARM/ARMRegisterBankInfo.cpp b/lib/Target/ARM/ARMRegisterBankInfo.cpp
index fad0e98285e..fb3553f318d 100644
--- a/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -263,7 +263,8 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case G_FADD:
   case G_FSUB:
   case G_FMUL:
-  case G_FDIV: {
+  case G_FDIV:
+  case G_FNEG: {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
     OperandsMapping =Ty.getSizeInBits() == 64
                           ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
diff --git a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
index 7821a65f120..049f4c60f86 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
@@ -59,6 +59,9 @@
   define void @test_fdiv_s32() #0 { ret void }
   define void @test_fdiv_s64() #0 { ret void }
 
+  define void @test_fneg_s32() #0 { ret void }
+  define void @test_fneg_s64() #0 { ret void }
+
   define void @test_soft_fp_s64() #0 { ret void }
 
   attributes #0 = { "target-features"="+vfp2"}
@@ -1093,6 +1096,52 @@ body:             |
 
 ...
 ---
+name:            test_fneg_s32
+# CHECK-LABEL: name: test_fneg_s32
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %s0
+
+    %0(s32) = COPY %s0
+    %1(s32) = G_FNEG %0
+    %s0 = COPY %1(s32)
+    BX_RET 14, %noreg, implicit %s0
+
+...
+---
+name:            test_fneg_s64
+# CHECK-LABEL: name: test_fneg_s64
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %d0
+
+    %0(s64) = COPY %d0
+    %1(s64) = G_FNEG %0
+    %d0 = COPY %1(s64)
+    BX_RET 14, %noreg, implicit %d0
+
+...
+---
 name:            test_soft_fp_s64
 # CHECK-LABEL: name: test_soft_fp_s64
 legalized:       true
-- 
2.11.0