From 9753f0b9b4ab33919c5010acb6a7b2dc1e875aff Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Tue, 28 Aug 2012 10:01:43 +0000 Subject: [PATCH] Teach InstCombine to canonicalize [SU]div+[AL]shl patterns. For example: %1 = lshr i32 %x, 2 %2 = udiv i32 %1, 100 rdar://12182093 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162743 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../InstCombine/InstCombineMulDivRem.cpp | 20 +++++++++ .../Transforms/InstCombine/2012-08-28-udiv_ashl.ll | 50 ++++++++++++++++++++++ test/Transforms/InstCombine/udiv-simplify-bug-1.ll | 4 +- 3 files changed, 72 insertions(+), 2 deletions(-) create mode 100644 test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll diff --git a/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index 35a0bbb7614..e104a0a9798 100644 --- a/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -462,6 +462,16 @@ Instruction *InstCombiner::visitUDiv(BinaryOperator &I) { } } + // Udiv ((Lshl x, c1) , c2) -> x / (C1 * 1<(Op1)) { + Value *X = 0, *C1 = 0; + if (match(Op0, m_LShr(m_Value(X), m_Value(C1)))) { + uint64_t NC = cast(C)->getZExtValue() * + (1<< cast(C1)->getZExtValue()); + return BinaryOperator::CreateUDiv(X, ConstantInt::get(I.getType(), NC)); + } + } + // X udiv (C1 << N), where C1 is "1< X >> (N+C2) { const APInt *CI; Value *N; if (match(Op1, m_Shl(m_Power2(CI), m_Value(N))) || @@ -533,6 +543,16 @@ Instruction *InstCombiner::visitSDiv(BinaryOperator &I) { ConstantExpr::getNeg(RHS)); } + // Sdiv ((Ashl x, c1) , c2) -> x / (C1 * 1<(Op1)) { + Value *X = 0, *C1 = 0; + if (match(Op0, m_AShr(m_Value(X), m_Value(C1)))) { + uint64_t NC = cast(C)->getZExtValue() * + (1<< cast(C1)->getZExtValue()); + return BinaryOperator::CreateSDiv(X, ConstantInt::get(I.getType(), NC)); + } + } + // If the sign bits of both operands are zero (i.e. we can prove they are // unsigned inputs), turn this into a udiv. if (I.getType()->isIntegerTy()) { diff --git a/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll b/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll new file mode 100644 index 00000000000..9f52119248e --- /dev/null +++ b/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll @@ -0,0 +1,50 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +; rdar://12182093 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; CHECK: @udiv400 +; CHECK: udiv i32 %x, 400 +; CHECK: ret +define i32 @udiv400(i32 %x) { +entry: + %div = lshr i32 %x, 2 + %div1 = udiv i32 %div, 100 + ret i32 %div1 +} + +; CHECK: @sdiv400 +; CHECK: sdiv i32 %x, 400 +; CHECK: ret +define i32 @sdiv400(i32 %x) { +entry: + %div = ashr i32 %x, 2 + %div1 = sdiv i32 %div, 100 + ret i32 %div1 +} + +; CHECK: @udiv400_no +; CHECK: ashr +; CHECK: div +; CHECK: ret +define i32 @udiv400_no(i32 %x) { +entry: + %div = ashr i32 %x, 2 + %div1 = udiv i32 %div, 100 + ret i32 %div1 +} + +; CHECK: @sdiv400_yes +; CHECK: udiv i32 %x, 400 +; CHECK: ret +define i32 @sdiv400_yes(i32 %x) { +entry: + %div = lshr i32 %x, 2 + ; The sign bits of both operands are zero (i.e. we can prove they are + ; unsigned inputs), turn this into a udiv. + ; Next, optimize this just like sdiv. + %div1 = sdiv i32 %div, 100 + ret i32 %div1 +} diff --git a/test/Transforms/InstCombine/udiv-simplify-bug-1.ll b/test/Transforms/InstCombine/udiv-simplify-bug-1.ll index d95e8f83590..74f2fdd7cc6 100644 --- a/test/Transforms/InstCombine/udiv-simplify-bug-1.ll +++ b/test/Transforms/InstCombine/udiv-simplify-bug-1.ll @@ -6,9 +6,9 @@ ; The udiv instructions shouldn't be optimized away, and the ; sext instructions should be optimized to zext. -define i64 @bar(i32 %x) nounwind { +define i64 @bar(i32 %x, i32 %g) nounwind { %y = lshr i32 %x, 30 - %r = udiv i32 %y, 3 + %r = udiv i32 %y, %g %z = sext i32 %r to i64 ret i64 %z } -- 2.11.0