From 9931d679675e45e14b7e8c49951b8849450c7b05 Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Thu, 30 Jun 2016 18:25:11 +0000 Subject: [PATCH] Delete MCCodeGenInfo. MC doesn't really care about CodeGen stuff, so this was just complicating target initialization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274258 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/ExecutionEngine/ExecutionEngine.h | 1 - include/llvm/MC/MCCodeGenInfo.h | 50 --------------- include/llvm/Support/TargetRegistry.h | 75 ++++------------------ include/llvm/Target/TargetMachine.h | 9 ++- lib/CodeGen/LLVMTargetMachine.cpp | 5 +- lib/MC/CMakeLists.txt | 1 - lib/MC/MCCodeGenInfo.cpp | 23 ------- .../AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp | 13 +--- .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp | 11 ---- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 12 ---- lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp | 12 ---- .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 14 ---- .../Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp | 14 ---- .../MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp | 14 ---- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp | 12 ---- .../NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp | 14 ---- .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 12 +--- .../Sparc/MCTargetDesc/SparcMCTargetDesc.cpp | 35 +++------- .../SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp | 16 ++--- lib/Target/TargetMachine.cpp | 30 ++------- .../MCTargetDesc/WebAssemblyMCTargetDesc.cpp | 12 +--- lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp | 13 +--- .../XCore/MCTargetDesc/XCoreMCTargetDesc.cpp | 15 ++--- 23 files changed, 59 insertions(+), 354 deletions(-) delete mode 100644 include/llvm/MC/MCCodeGenInfo.h delete mode 100644 lib/MC/MCCodeGenInfo.cpp diff --git a/include/llvm/ExecutionEngine/ExecutionEngine.h b/include/llvm/ExecutionEngine/ExecutionEngine.h index 9518e5ad37d..ab13028b3ae 100644 --- a/include/llvm/ExecutionEngine/ExecutionEngine.h +++ b/include/llvm/ExecutionEngine/ExecutionEngine.h @@ -22,7 +22,6 @@ #include "llvm/IR/Module.h" #include "llvm/IR/ValueHandle.h" #include "llvm/IR/ValueMap.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/Object/Binary.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Mutex.h" diff --git a/include/llvm/MC/MCCodeGenInfo.h b/include/llvm/MC/MCCodeGenInfo.h deleted file mode 100644 index b71cdf90b24..00000000000 --- a/include/llvm/MC/MCCodeGenInfo.h +++ /dev/null @@ -1,50 +0,0 @@ -//===-- llvm/MC/MCCodeGenInfo.h - Target CodeGen Info -----------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file tracks information about the target which can affect codegen, -// asm parsing, and asm printing. For example, relocation model. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_MC_MCCODEGENINFO_H -#define LLVM_MC_MCCODEGENINFO_H - -#include "llvm/Support/CodeGen.h" - -namespace llvm { - -class MCCodeGenInfo { - /// Relocation model: static, pic, etc. - /// - Reloc::Model RelocationModel; - - /// Code model. - /// - CodeModel::Model CMModel; - - /// Optimization level. - /// - CodeGenOpt::Level OptLevel; - -public: - void initMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, - CodeGenOpt::Level OL); - - Reloc::Model getRelocationModel() const { return RelocationModel; } - - CodeModel::Model getCodeModel() const { return CMModel; } - - CodeGenOpt::Level getOptLevel() const { return OptLevel; } - - // Allow overriding OptLevel on a per-function basis. - void setOptLevel(CodeGenOpt::Level Level) { OptLevel = Level; } -}; -} // namespace llvm - -#endif diff --git a/include/llvm/Support/TargetRegistry.h b/include/llvm/Support/TargetRegistry.h index a8e9f54e12d..076558e4df7 100644 --- a/include/llvm/Support/TargetRegistry.h +++ b/include/llvm/Support/TargetRegistry.h @@ -34,7 +34,6 @@ class MCAsmBackend; class MCAsmInfo; class MCAsmParser; class MCCodeEmitter; -class MCCodeGenInfo; class MCContext; class MCDisassembler; class MCInstrAnalysis; @@ -93,10 +92,9 @@ public: typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI, const Triple &TT); - typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(const Triple &TT, - Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL); + typedef void (*MCAdjustCodeGenOptsFnTy)(const Triple &TT, Reloc::Model RM, + CodeModel::Model &CM); + typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo *Info); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(const Triple &TT); @@ -178,9 +176,7 @@ private: /// registered. MCAsmInfoCtorFnTy MCAsmInfoCtorFn; - /// MCCodeGenInfoCtorFn - Constructor function for this target's - /// MCCodeGenInfo, if registered. - MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn; + MCAdjustCodeGenOptsFnTy MCAdjustCodeGenOptsFn; /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo, /// if registered. @@ -301,14 +297,10 @@ public: return MCAsmInfoCtorFn(MRI, Triple(TheTriple)); } - /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation. - /// - MCCodeGenInfo *createMCCodeGenInfo(StringRef TT, Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) const { - if (!MCCodeGenInfoCtorFn) - return nullptr; - return MCCodeGenInfoCtorFn(Triple(TT), RM, CM, OL); + void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, + CodeModel::Model &CM) const { + if (MCAdjustCodeGenOptsFn) + MCAdjustCodeGenOptsFn(TT, RM, CM); } /// createMCInstrInfo - Create a MCInstrInfo implementation. @@ -646,18 +638,9 @@ struct TargetRegistry { T.MCAsmInfoCtorFn = Fn; } - /// RegisterMCCodeGenInfo - Register a MCCodeGenInfo implementation for the - /// given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct a MCCodeGenInfo for the target. - static void RegisterMCCodeGenInfo(Target &T, - Target::MCCodeGenInfoCtorFnTy Fn) { - T.MCCodeGenInfoCtorFn = Fn; + static void registerMCAdjustCodeGenOpts(Target &T, + Target::MCAdjustCodeGenOptsFnTy Fn) { + T.MCAdjustCodeGenOptsFn = Fn; } /// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the @@ -914,39 +897,9 @@ struct RegisterMCAsmInfoFn { } }; -/// RegisterMCCodeGenInfo - Helper template for registering a target codegen -/// info -/// implementation. This invokes the static "Create" method on the class -/// to actually do the construction. Usage: -/// -/// extern "C" void LLVMInitializeFooTarget() { -/// extern Target TheFooTarget; -/// RegisterMCCodeGenInfo X(TheFooTarget); -/// } -template struct RegisterMCCodeGenInfo { - RegisterMCCodeGenInfo(Target &T) { - TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator); - } - -private: - static MCCodeGenInfo *Allocator(const Triple & /*TT*/, Reloc::Model /*RM*/, - CodeModel::Model /*CM*/, - CodeGenOpt::Level /*OL*/) { - return new MCCodeGenInfoImpl(); - } -}; - -/// RegisterMCCodeGenInfoFn - Helper template for registering a target codegen -/// info implementation. This invokes the specified function to do the -/// construction. Usage: -/// -/// extern "C" void LLVMInitializeFooTarget() { -/// extern Target TheFooTarget; -/// RegisterMCCodeGenInfoFn X(TheFooTarget, TheFunction); -/// } -struct RegisterMCCodeGenInfoFn { - RegisterMCCodeGenInfoFn(Target &T, Target::MCCodeGenInfoCtorFnTy Fn) { - TargetRegistry::RegisterMCCodeGenInfo(T, Fn); +struct RegisterMCAdjustCodeGenOptsFn { + RegisterMCAdjustCodeGenOptsFn(Target &T, Target::MCAdjustCodeGenOptsFnTy Fn) { + TargetRegistry::registerMCAdjustCodeGenOpts(T, Fn); } }; diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index 79897b27f2e..563fef96acf 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -31,7 +31,6 @@ class Mangler; class MachineFunctionInitializer; class MachineModuleInfo; class MCAsmInfo; -class MCCodeGenInfo; class MCContext; class MCInstrInfo; class MCRegisterInfo; @@ -89,9 +88,9 @@ protected: // Can only create subclasses. std::string TargetCPU; std::string TargetFS; - /// Low level target information such as relocation model. Non-const to - /// allow resetting optimization level per-function. - MCCodeGenInfo *CodeGenInfo; + Reloc::Model RM = Reloc::Static; + CodeModel::Model CMModel = CodeModel::Default; + CodeGenOpt::Level OptLevel = CodeGenOpt::Default; /// Contains target specific asm information. const MCAsmInfo *AsmInfo; @@ -186,7 +185,7 @@ public: CodeGenOpt::Level getOptLevel() const; /// \brief Overrides the optimization level. - void setOptLevel(CodeGenOpt::Level Level) const; + void setOptLevel(CodeGenOpt::Level Level); void setFastISel(bool Enable) { Options.EnableFastISel = Enable; } bool getO0WantsFastISel() { return O0WantsFastISel; } diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index b164cad7d14..f6f9b740957 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -88,7 +88,10 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) : TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) { - CodeGenInfo = T.createMCCodeGenInfo(TT.str(), RM, CM, OL); + T.adjustCodeGenOpts(TT, RM, CM); + this->RM = RM; + this->CMModel = CM; + this->OptLevel = OL; } TargetIRAnalysis LLVMTargetMachine::getTargetIRAnalysis() { diff --git a/lib/MC/CMakeLists.txt b/lib/MC/CMakeLists.txt index 698dc9fa0b2..2f1b39e58e3 100644 --- a/lib/MC/CMakeLists.txt +++ b/lib/MC/CMakeLists.txt @@ -9,7 +9,6 @@ add_llvm_library(LLVMMC MCAsmStreamer.cpp MCAssembler.cpp MCCodeEmitter.cpp - MCCodeGenInfo.cpp MCCodeView.cpp MCContext.cpp MCDwarf.cpp diff --git a/lib/MC/MCCodeGenInfo.cpp b/lib/MC/MCCodeGenInfo.cpp deleted file mode 100644 index 347ec2cd01e..00000000000 --- a/lib/MC/MCCodeGenInfo.cpp +++ /dev/null @@ -1,23 +0,0 @@ -//===-- MCCodeGenInfo.cpp - Target CodeGen Info -----------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file tracks information about the target which can affect codegen, -// asm parsing, and asm printing. For example, relocation model. -// -//===----------------------------------------------------------------------===// - -#include "llvm/MC/MCCodeGenInfo.h" -using namespace llvm; - -void MCCodeGenInfo::initMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, - CodeGenOpt::Level OL) { - RelocationModel = RM; - CMModel = CM; - OptLevel = OL; -} diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp index 6c1784b4b8a..70278062120 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -15,7 +15,6 @@ #include "AArch64ELFStreamer.h" #include "AArch64MCAsmInfo.h" #include "InstPrinter/AArch64InstPrinter.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" @@ -72,10 +71,8 @@ static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createAArch64MCCodeGenInfo(const Triple &TT, - Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { +static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, + CodeModel::Model &CM) { assert((TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()) && "Only expect Darwin and ELF targets"); @@ -89,10 +86,6 @@ static MCCodeGenInfo *createAArch64MCCodeGenInfo(const Triple &TT, else if (CM != CodeModel::Small && CM != CodeModel::Large) report_fatal_error( "Only small and large code models are allowed on AArch64"); - - MCCodeGenInfo *X = new MCCodeGenInfo(); - X->initMCCodeGenInfo(RM, CM, OL); - return X; } static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T, @@ -131,7 +124,7 @@ extern "C" void LLVMInitializeAArch64TargetMC() { RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(*T, createAArch64MCCodeGenInfo); + TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts); // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo); diff --git a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp index f7040947027..a0d9aab114f 100644 --- a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -18,7 +18,6 @@ #include "AMDGPUTargetStreamer.h" #include "InstPrinter/AMDGPUInstPrinter.h" #include "SIDefines.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -56,15 +55,6 @@ createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS); } -static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const Triple &TT, - Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - X->initMCCodeGenInfo(RM, CM, OL); - return X; -} - static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, @@ -99,7 +89,6 @@ extern "C" void LLVMInitializeAMDGPUTargetMC() { for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) { RegisterMCAsmInfo X(*T); - TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo); TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo); TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo); TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo); diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index e50025dd1f5..afb089ab028 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -16,7 +16,6 @@ #include "ARMMCTargetDesc.h" #include "InstPrinter/ARMInstPrinter.h" #include "llvm/ADT/Triple.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" @@ -201,14 +200,6 @@ static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - X->initMCCodeGenInfo(RM, CM, OL); - return X; -} - static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll) { @@ -287,9 +278,6 @@ extern "C" void LLVMInitializeARMTargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo); - // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(*T, createARMMCCodeGenInfo); - // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo); diff --git a/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp b/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp index 840570ebc39..03d6b193fe2 100644 --- a/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp +++ b/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp @@ -15,7 +15,6 @@ #include "BPFMCTargetDesc.h" #include "BPFMCAsmInfo.h" #include "InstPrinter/BPFInstPrinter.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" @@ -51,14 +50,6 @@ static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT, return createBPFMCSubtargetInfoImpl(TT, CPU, FS); } -static MCCodeGenInfo *createBPFMCCodeGenInfo(const Triple &TT, Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - X->initMCCodeGenInfo(RM, CM, OL); - return X; -} - static MCStreamer *createBPFMCStreamer(const Triple &T, MCContext &Ctx, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, @@ -81,9 +72,6 @@ extern "C" void LLVMInitializeBPFTargetMC() { // Register the MC asm info. RegisterMCAsmInfo X(*T); - // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(*T, createBPFMCCodeGenInfo); - // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createBPFMCInstrInfo); diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 3088bd7bfbb..35a1a23a889 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -16,7 +16,6 @@ #include "HexagonMCAsmInfo.h" #include "HexagonMCELFStreamer.h" #include "MCTargetDesc/HexagonInstPrinter.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCInstrInfo.h" @@ -199,15 +198,6 @@ static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createHexagonMCCodeGenInfo(const Triple &TT, - Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - X->initMCCodeGenInfo(RM, CM, OL); - return X; -} - static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, @@ -242,10 +232,6 @@ extern "C" void LLVMInitializeHexagonTargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo); - // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(TheHexagonTarget, - createHexagonMCCodeGenInfo); - // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget, createHexagonMCInstrInfo); diff --git a/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp b/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp index 9db240100b4..3bc2e8bc2c3 100644 --- a/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp +++ b/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp @@ -15,7 +15,6 @@ #include "InstPrinter/LanaiInstPrinter.h" #include "LanaiMCAsmInfo.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCStreamer.h" @@ -55,15 +54,6 @@ createLanaiMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createLanaiMCSubtargetInfoImpl(TT, CPUName, FS); } -static MCCodeGenInfo *createLanaiMCCodeGenInfo(const Triple &TT, - Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - X->initMCCodeGenInfo(RM, CM, OL); - return X; -} - static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll) { @@ -125,10 +115,6 @@ extern "C" void LLVMInitializeLanaiTargetMC() { // Register the MC asm info. RegisterMCAsmInfo X(TheLanaiTarget); - // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(TheLanaiTarget, - createLanaiMCCodeGenInfo); - // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(TheLanaiTarget, createLanaiMCInstrInfo); diff --git a/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp b/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp index 807d1129b5f..b3631caca95 100644 --- a/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp +++ b/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -14,7 +14,6 @@ #include "MSP430MCTargetDesc.h" #include "InstPrinter/MSP430InstPrinter.h" #include "MSP430MCAsmInfo.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" @@ -48,15 +47,6 @@ createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createMSP430MCSubtargetInfoImpl(TT, CPU, FS); } -static MCCodeGenInfo *createMSP430MCCodeGenInfo(const Triple &TT, - Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - X->initMCCodeGenInfo(RM, CM, OL); - return X; -} - static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, @@ -71,10 +61,6 @@ extern "C" void LLVMInitializeMSP430TargetMC() { // Register the MC asm info. RegisterMCAsmInfo X(TheMSP430Target); - // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(TheMSP430Target, - createMSP430MCCodeGenInfo); - // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, createMSP430MCInstrInfo); diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index dbb6f1f0bba..a0557395097 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -18,7 +18,6 @@ #include "MipsMCNaCl.h" #include "MipsTargetStreamer.h" #include "llvm/ADT/Triple.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" @@ -82,14 +81,6 @@ static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - X->initMCCodeGenInfo(RM, CM, OL); - return X; -} - static MCInstPrinter *createMipsMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, @@ -163,9 +154,6 @@ extern "C" void LLVMInitializeMipsTargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); - // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo); - // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo); diff --git a/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp b/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp index a57ef2a102c..e356a965a04 100644 --- a/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp +++ b/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp @@ -14,7 +14,6 @@ #include "NVPTXMCTargetDesc.h" #include "InstPrinter/NVPTXInstPrinter.h" #include "NVPTXMCAsmInfo.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" @@ -49,16 +48,6 @@ createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createNVPTXMCSubtargetInfoImpl(TT, CPU, FS); } -static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const Triple &TT, - Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - - X->initMCCodeGenInfo(RM, CM, OL); - return X; -} - static MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, @@ -75,9 +64,6 @@ extern "C" void LLVMInitializeNVPTXTargetMC() { // Register the MC asm info. RegisterMCAsmInfo X(*T); - // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(*T, createNVPTXMCCodeGenInfo); - // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createNVPTXMCInstrInfo); diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp index d3031c686aa..c9074448fe4 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -15,7 +15,6 @@ #include "InstPrinter/PPCInstPrinter.h" #include "PPCMCAsmInfo.h" #include "PPCTargetStreamer.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCExpr.h" @@ -87,18 +86,13 @@ static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createPPCMCCodeGenInfo(const Triple &TT, Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - +static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, + CodeModel::Model &CM) { if (CM == CodeModel::Default) { if (!TT.isOSDarwin() && (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le)) CM = CodeModel::Medium; } - X->initMCCodeGenInfo(RM, CM, OL); - return X; } namespace { @@ -239,7 +233,7 @@ extern "C" void LLVMInitializePowerPCTargetMC() { RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo); // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(*T, createPPCMCCodeGenInfo); + TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts); // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createPPCMCInstrInfo); diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index 9113e4a46b9..dceaca791aa 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -15,7 +15,6 @@ #include "InstPrinter/SparcInstPrinter.h" #include "SparcMCAsmInfo.h" #include "SparcTargetStreamer.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" @@ -81,12 +80,8 @@ createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { // // All code models require that the text segment is smaller than 2GB. -static MCCodeGenInfo *createSparcMCCodeGenInfo(const Triple &TT, - Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - +static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, + CodeModel::Model &CM) { // The default 32-bit code model is abs32/pic32 and the default 32-bit // code model for JIT is abs32. switch (CM) { @@ -94,17 +89,10 @@ static MCCodeGenInfo *createSparcMCCodeGenInfo(const Triple &TT, case CodeModel::Default: case CodeModel::JITDefault: CM = CodeModel::Small; break; } - - X->initMCCodeGenInfo(RM, CM, OL); - return X; } -static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const Triple &TT, - Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - +static void adjustCodeGenOptsV9(const Triple &TT, Reloc::Model RM, + CodeModel::Model &CM) { // The default 64-bit code model is abs44/pic32 and the default 64-bit // code model for JIT is abs64. switch (CM) { @@ -116,9 +104,6 @@ static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const Triple &TT, CM = CodeModel::Large; break; } - - X->initMCCodeGenInfo(RM, CM, OL); - return X; } static MCTargetStreamer * @@ -175,10 +160,10 @@ extern "C" void LLVMInitializeSparcTargetMC() { } // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget, - createSparcMCCodeGenInfo); - TargetRegistry::RegisterMCCodeGenInfo(TheSparcV9Target, - createSparcV9MCCodeGenInfo); - TargetRegistry::RegisterMCCodeGenInfo(TheSparcelTarget, - createSparcMCCodeGenInfo); + TargetRegistry::registerMCAdjustCodeGenOpts(TheSparcTarget, + adjustCodeGenOpts); + TargetRegistry::registerMCAdjustCodeGenOpts(TheSparcV9Target, + adjustCodeGenOptsV9); + TargetRegistry::registerMCAdjustCodeGenOpts(TheSparcelTarget, + adjustCodeGenOpts); } diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp index 4c7cdbc645d..e16ba9e1531 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -10,7 +10,6 @@ #include "SystemZMCTargetDesc.h" #include "InstPrinter/SystemZInstPrinter.h" #include "SystemZMCAsmInfo.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" @@ -159,11 +158,8 @@ createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createSystemZMCSubtargetInfoImpl(TT, CPU, FS); } -static MCCodeGenInfo *createSystemZMCCodeGenInfo(const Triple &TT, - Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); +static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, + CodeModel::Model &CM) { // For SystemZ we define the models as follows: // // Small: BRASL can call any function and will use a stub if necessary. @@ -197,8 +193,6 @@ static MCCodeGenInfo *createSystemZMCCodeGenInfo(const Triple &TT, CM = CodeModel::Small; else if (CM == CodeModel::JITDefault) CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; - X->initMCCodeGenInfo(RM, CM, OL); - return X; } static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T, @@ -214,9 +208,9 @@ extern "C" void LLVMInitializeSystemZTargetMC() { TargetRegistry::RegisterMCAsmInfo(TheSystemZTarget, createSystemZMCAsmInfo); - // Register the MCCodeGenInfo. - TargetRegistry::RegisterMCCodeGenInfo(TheSystemZTarget, - createSystemZMCCodeGenInfo); + // Register the adjustCodeGenOpts. + TargetRegistry::registerMCAdjustCodeGenOpts(TheSystemZTarget, + adjustCodeGenOpts); // Register the MCCodeEmitter. TargetRegistry::RegisterMCCodeEmitter(TheSystemZTarget, diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp index aea87486d70..ed2f4fef0f0 100644 --- a/lib/Target/TargetMachine.cpp +++ b/lib/Target/TargetMachine.cpp @@ -21,7 +21,6 @@ #include "llvm/IR/LegacyPassManager.h" #include "llvm/IR/Mangler.h" #include "llvm/MC/MCAsmInfo.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCSectionMachO.h" @@ -40,12 +39,10 @@ TargetMachine::TargetMachine(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options) : TheTarget(T), DL(DataLayoutString), TargetTriple(TT), TargetCPU(CPU), - TargetFS(FS), CodeGenInfo(nullptr), AsmInfo(nullptr), MRI(nullptr), - MII(nullptr), STI(nullptr), RequireStructuredCFG(false), - Options(Options) {} + TargetFS(FS), AsmInfo(nullptr), MRI(nullptr), MII(nullptr), STI(nullptr), + RequireStructuredCFG(false), Options(Options) {} TargetMachine::~TargetMachine() { - delete CodeGenInfo; delete AsmInfo; delete MRI; delete MII; @@ -77,19 +74,11 @@ void TargetMachine::resetTargetOptions(const Function &F) const { /// Returns the code generation relocation model. The choices are static, PIC, /// and dynamic-no-pic. -Reloc::Model TargetMachine::getRelocationModel() const { - if (!CodeGenInfo) - return Reloc::Static; // FIXME - return CodeGenInfo->getRelocationModel(); -} +Reloc::Model TargetMachine::getRelocationModel() const { return RM; } /// Returns the code model. The choices are small, kernel, medium, large, and /// target default. -CodeModel::Model TargetMachine::getCodeModel() const { - if (!CodeGenInfo) - return CodeModel::Default; - return CodeGenInfo->getCodeModel(); -} +CodeModel::Model TargetMachine::getCodeModel() const { return CMModel; } /// Get the IR-specified TLS model for Var. static TLSModel::Model getSelectedTLSModel(const GlobalValue *GV) { @@ -182,16 +171,9 @@ TLSModel::Model TargetMachine::getTLSModel(const GlobalValue *GV) const { } /// Returns the optimization level: None, Less, Default, or Aggressive. -CodeGenOpt::Level TargetMachine::getOptLevel() const { - if (!CodeGenInfo) - return CodeGenOpt::Default; - return CodeGenInfo->getOptLevel(); -} +CodeGenOpt::Level TargetMachine::getOptLevel() const { return OptLevel; } -void TargetMachine::setOptLevel(CodeGenOpt::Level Level) const { - if (CodeGenInfo) - CodeGenInfo->setOptLevel(Level); -} +void TargetMachine::setOptLevel(CodeGenOpt::Level Level) { OptLevel = Level; } TargetIRAnalysis TargetMachine::getTargetIRAnalysis() { return TargetIRAnalysis([this](const Function &F) { diff --git a/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp b/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp index a7a813313a2..ac11a64086f 100644 --- a/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp +++ b/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp @@ -16,7 +16,6 @@ #include "InstPrinter/WebAssemblyInstPrinter.h" #include "WebAssemblyMCAsmInfo.h" #include "WebAssemblyTargetStreamer.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" @@ -40,18 +39,13 @@ static MCAsmInfo *createMCAsmInfo(const MCRegisterInfo & /*MRI*/, return new WebAssemblyMCAsmInfo(TT); } -static MCCodeGenInfo *createMCCodeGenInfo(const Triple & /*TT*/, - Reloc::Model /*RM*/, - CodeModel::Model CM, - CodeGenOpt::Level OL) { +static void adjustCodeGenOpts(const Triple & /*TT*/, Reloc::Model /*RM*/, + CodeModel::Model &CM) { CodeModel::Model M = (CM == CodeModel::Default || CM == CodeModel::JITDefault) ? CodeModel::Large : CM; if (M != CodeModel::Large) report_fatal_error("Non-large code models are not supported yet"); - MCCodeGenInfo *CGI = new MCCodeGenInfo(); - CGI->initMCCodeGenInfo(Reloc::PIC_, CM, OL); - return CGI; } static MCInstrInfo *createMCInstrInfo() { @@ -114,7 +108,7 @@ extern "C" void LLVMInitializeWebAssemblyTargetMC() { TargetRegistry::RegisterMCInstrInfo(*T, createMCInstrInfo); // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(*T, createMCCodeGenInfo); + TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts); // Register the MC register info. TargetRegistry::RegisterMCRegInfo(*T, createMCRegisterInfo); diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp index 8f34c5b09c8..311a8d677ee 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -16,7 +16,6 @@ #include "InstPrinter/X86IntelInstPrinter.h" #include "X86MCAsmInfo.h" #include "llvm/ADT/Triple.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -199,11 +198,8 @@ static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - +static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, + CodeModel::Model &CM) { bool is64Bit = TT.getArch() == Triple::x86_64; // For static codegen, if we're not already set, use Small codegen. @@ -212,9 +208,6 @@ static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM, else if (CM == CodeModel::JITDefault) // 64-bit JIT places everything in the same buffer except external funcs. CM = is64Bit ? CodeModel::Large : CodeModel::Small; - - X->initMCCodeGenInfo(RM, CM, OL); - return X; } static MCInstPrinter *createX86MCInstPrinter(const Triple &T, @@ -246,7 +239,7 @@ extern "C" void LLVMInitializeX86TargetMC() { RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); // Register the MC codegen info. - RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo); + RegisterMCAdjustCodeGenOptsFn Y(*T, adjustCodeGenOpts); // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp index cd3c65dfde1..63ca1e7d464 100644 --- a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -15,7 +15,6 @@ #include "InstPrinter/XCoreInstPrinter.h" #include "XCoreMCAsmInfo.h" #include "XCoreTargetStreamer.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" @@ -62,19 +61,13 @@ static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createXCoreMCCodeGenInfo(const Triple &TT, - Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); +static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, + CodeModel::Model &CM) { if (CM == CodeModel::Default) { CM = CodeModel::Small; } if (CM != CodeModel::Small && CM != CodeModel::Large) report_fatal_error("Target only supports CodeModel Small or Large"); - - X->initMCCodeGenInfo(RM, CM, OL); - return X; } static MCInstPrinter *createXCoreMCInstPrinter(const Triple &T, @@ -134,8 +127,8 @@ extern "C" void LLVMInitializeXCoreTargetMC() { RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo); // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(TheXCoreTarget, - createXCoreMCCodeGenInfo); + TargetRegistry::registerMCAdjustCodeGenOpts(TheXCoreTarget, + adjustCodeGenOpts); // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo); -- 2.11.0